Preliminary Technical Data
FEATURES
2 pF off capacitance
1 pC charge injection
33 V supply range
150 Ω on resistance
Fully specified at +12 V, ±15 V
No V
L
supply required
3 V logic-compatible inputs
Rail-to-rail operation
16-lead TSSOP and 16-lead LFCSP packages
Typical power consumption: <0.03 µW
1 pF Off Capacitance, 1 pC Charge Injection,
±15 V/12 V
iCMOS™
Quad SPST Switches
ADG1211/ADG1212/ADG1213
FUNCTIONAL BLOCK DIAGRAM
S1
IN1
D1
S2
IN2
IN2
D2
S3
IN3
D3
S4
IN4
D4
IN4
D4
IN3
D3
S4
IN4
04778-0-001
S1
IN1
D1
S2
IN2
D2
S3
IN3
IN1
S1
D1
S2
D2
ADG1211
ADG1212
ADG1213
S3
D3
S4
D4
SWITCHES SHOWN FOR A LOGIC 1 INPUT
APPLICATIONS
Automatic test equipment
Data aquisition systems
Battery-powered systems
Sample-and-hold systems
Audio signal routing
Video signal routing
Communication systems
Figure 1.
iCMOS
construction ensures ultralow power dissipation,
making the parts ideally suited for portable and battery-
powered instruments.
The ADG1211/ADG1212/ADG1213 contain four independent
single-pole/single-throw (SPST) switches. The ADG1211 and
ADG1212 differ only in that the digital control logic is inverted.
The ADG1211 switches are turned on with Logic 0 on the
appropriate control input, while Logic 1 is required for the
ADG1212. The ADG1213 has two switches with digital control
logic similar to that of the ADG1211; the logic is inverted on the
other two switches. Each switch conducts equally well in both
directions when on, and has an input signal range that extends
to the supplies. In the off condition, signal levels up to the
supplies are blocked.
The ADG1213 exhibits break-before-make switching action for
use in multiplexer applications. Inherent in the design is low
charge injection for minimum transients when switching the
digital inputs.
GENERAL DESCRIPTION
The ADG1211/ADG1212/ADG1213 are monolithic CMOS
devices containing four independently selectable switches
designed on an
iCMOS
process.
iCMOS
(industrial-CMOS) is a
modular manufacturing process combining high voltage CMOS
(complementary metal-oxide semiconductor) and bipolar
technologies. It enables the development of a wide range of high
performance analog ICs capable of 30 V operation in a footprint
that no previous generation of high voltage parts has been able
to achieve. Unlike analog ICs using conventional CMOS proc-
esses,
iCMOS
components can tolerate high supply voltages,
while providing increased performance, dramatically lower
power consumption, and reduced package size.
The ultralow capacitance and charge injection of these switches
make them ideal solutions for data acquisition and sample-and-
hold applications, where low glitch and fast settling are required.
Fast switching speed coupled with high signal bandwidth make
the parts suitable for video signal switching.
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
5.
6.
2 pF off capacitance (±15 V supply).
1 pC charge injection.
3 V logic-compatible digital inputs: V
IH
= 2.0 V, V
IL
= 0.8 V.
No V
L
logic power supply required.
Ultralow power dissipation: <0.03 µW.
16-lead TSSOP and 4 mm × 4 mm LFCSP packages.
Rev. PrE
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703
© 2004 Analog Devices, Inc. All rights reserved.
ADG1211/ADG1212/ADG1213
TABLE OF CONTENTS
Specifications..................................................................................... 3
Single Supply ................................................................................. 3
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configurations and Function Descriptions ........................... 7
Preliminary Technical Data
Terminology .......................................................................................8
Typical Performance Characteristics ..............................................9
Test Circuits..................................................................................... 12
Outline Dimensions ....................................................................... 14
Ordering Guide .......................................................................... 14
REVISION HISTORY
11/04—Revision PrE: Preliminary Version
Rev. PrE | Page 2 of 16
Preliminary Technical Data
SPECIFICATIONS
SINGLE SUPPLY
V
DD
= 15 V ± 10%, V
SS
=
−15
V, GND = 0 V, unless otherwise noted.
Table 1.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance (R
ON
)
On Resistance Match between
Channels (∆R
ON
)
On Resistance Flatness (R
FLAT(ON)
)
LEAKAGE CURRENTS
Source Off Leakage, I
S
(Off)
Drain Off Leakage, I
D
(Off)
25°C
85°C
Y Version
1
V
DD
to V
SS
180
Unit
ADADG1211/ADG1212/ADG1213
Test Conditions/Comments
120
5
160
V
Ω
typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
nA typ
nA max
nA typ
nA max
nA typ
V
S
= ±10 V, I
S
= −10 mA; Figure 20
V
S
= ±10 V , I
S
= −10 mA
25
50
±0.01
±0.5
±0.01
±0.5
V
S
= −5 V/0 V/+5 V; I
S
= −10 mA
V
DD
= +10 V, V
SS
= −10 V
V
S
= 0 V/10 V, V
D
= 10 V/0 V; Figure 21
V
S
= 0 V/10 V, V
D
= 10 V/0 V; Figure 21
±1
±5
±1
±5
Channel On Leakage, I
D
, I
S
(On)
±0.04
±1
V
S
= V
D
= 0 V or 10 V; Figure 22
±2
±5
2.0
0.8
±2.5
±0.5
nA max
DIGITAL INPUTS
Input High Voltage, V
INH
Input Low Voltage, V
INL
Input Current, I
INL
or I
INH
Digital Input Capacitance, C
IN
DYNAMIC CHARACTERISTICS
2
t
ON
t
OFF
Break-before-Make Time Delay, t
D
Charge Injection
Off Isolation
Channel-to-Channel Crosstalk
Total Harmonic Distortion + Noise
−3 dB Bandwidth
C
S
(Off)
C
D
(Off)
C
D
, C
S
(On)
POWER REQUIREMENTS
I
DD
I
DD
I
SS
0.005
5
50
15
15
V min
V max
µA typ
µA max
pF typ
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
dB typ
dB typ
% typ
MHz typ
pF typ
pF typ
pF typ
µA typ
µA max
µA typ
µA max
µA typ
µA max
V
IN
= V
INL
or V
INH
1
1
75
85
0.002
700
2
2
4
0.001
5.0
0.001
5.0
0.001
5.0
Rev. PrE | Page 3 of 16
R
L
= 300 Ω, C
L
= 35 pF
V
S
= ±10 V; Figure 23
R
L
= 300 Ω, C
L
= 35 pF
V
S
= ±10 V; Figure 23
R
L
= 300 Ω, C
L
= 35 pF
V
S1
= V
S2
= 10 V; Figure 24
V
S
= 0 V, R
S
= 0 Ω, C
L
= 1 nF; Figure 25
R
L
= 50 Ω, C
L
= 5 pF, f = 1 MHz; Figure 26
R
L
= 50 Ω, C
L
= 5 pF, f = 1 MHz; Figure 27
R
L
= 600 Ω, 5 V rms, f = 20 Hz to 20 kHz
R
L
= 50 Ω, C
L
= 5 pF; Figure 28
V
DD
= +16.5 V, V
SS
= −16.5 V
Digital Inputs = 0 V or V
DD
Digital Inputs = 5 V
Digital Inputs = 0 V or V
DD
ADG1211/ADG1212/ADG1213
Parameter
I
GND
I
GND
25°C
0.001
0.001
5.0
Temperature range for Y Version is
−40°C
to +125°C.
Guaranteed by design, not subject to production test.
Preliminary Technical Data
85°C
Y Version
1
5.0
Unit
µA typ
µA max
µA typ
µA max
Test Conditions/Comments
Digital Inputs = 0 V or V
DD
Digital Inputs = 5 V
1
2
V
DD
= 12 V ± 10%, V
SS
= 0 V, GND = 0 V, unless otherwise noted.
Table 2.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance (R
ON
)
On Resistance Match between
Channels (∆R
ON
)
On -Resistance Flatness (R
FLAT(ON)
)
LEAKAGE CURRENTS
Source Off Leakage, I
S
(Off)
Drain Off Leakage, I
D
(Off)
Channel On Leakage, I
D
, I
S
(On)
DIGITAL INPUTS
Input High Voltage, V
INH
Input Low Voltage, V
INL
Input Current, I
INL
or I
INH
Digital Input Capacitance, C
IN
DYNAMIC CHARACTERISTICS
2
t
ON
t
OFF
Break-before-Make Time Delay, t
D
Charge Injection
Off Isolation
Channel-to-Channel Crosstalk
−3 dB Bandwidth
C
S
(Off)
C
D
(Off)
C
D
, C
S
(On)
25°C
85°C
Y Version
1
0 V to V
DD
220
1
250
Unit
V
Ω typ
Ω max
Ω typ
Ω max
Ω typ
nA typ
nA max
nA typ
nA max
nA typ
nA max
V min
V max
µA typ
µA max
pF typ
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
dB typ
dB typ
MHz typ
pF typ
pF typ
pF typ
Test Conditions/Comments
V
S
= +10 V, I
S
= −10 mA; Figure 20
V
S
= +10 V, I
S
= −10 mA
12
±0.01
±0.5
±0.01
±0.5
±0.04
±1
V
S
= −5 V/0 V/+5 V, I
S
= −10 mA
V
DD
= 12 V
V
S
= 1 V/10 V, V
D
= 10 V/0 V; Figure 21
V
S
= 1 V/10 V, V
D
= 10 V/0 V; Figure 21
V
S
= V
D
= 1 V or 10 V; Figure 22
±2.5
±2.5
±5
2.0
0.8
0.001
±0.5
5
50
15
15
1
5
75
85
100
2
2
4
V
IN
= V
INL
or V
INH
R
L
= 300 Ω, C
L
= 35 pF
V
S
= 8 V; Figure 23
R
L
= 300 Ω, C
L
= 35 pF
V
S
= 8 V; Figure 23
R
L
= 300 Ω, C
L
= 35 pF
V
S1
= V
S2
= 8 V; Figure 24
V
S
= 0 V, R
S
= 0 Ω, C
L
= 1 nF; Figure 25
R
L
= 50 Ω, C
L
= 5 pF, f = 1 MHz; Figure 267
R
L
= 50 Ω, C
L
= 5 pF, f = 1 MHz; Figure 27
R
L
= 50 Ω, C
L
= 5 pF; Figure 28
Rev. PrE | Page 4 of 16
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