Register Map: Section
5.2
ZL40250–ZL40253 SmartBuffer
TM
6- or 10-Output Programmable Fanout
Buffers with Multi-Format I/O and Dividers
Data Sheet
September 2018
Features
•
Four Flexible Input Clocks
•
One crystal/CMOS input
•
Two differential/CMOS inputs
•
One single-ended/CMOS input
•
Any input frequency up to 1GHz (300MHz for
CMOS)
•
Manual clock switching by pin or register
•
6 or 10 Universal Output Clocks with Dividers
•
Each output has independent divider
•
Low additive jitter <200fs RMS (12kHz-20MHz,
for input frequencies
100MHz)
•
Each output configurable as LVDS, LVPECL,
HCSL, 2xCMOS or HSTL
•
In 2xCMOS mode, the P and N pins can be
different frequencies (e.g. 125MHz and 25MHz)
*
•
Multiple output supply voltage banks with
CMOS output voltages from 1.5V to 3.3V
•
Precise output alignment circuitry from GPIO
pin or register bit
*
•
Per-output skew adjustment
*
•
Per-output enable/disable and glitchless
start/stop (stop high or low)
*
•
ZL40250LDG1
ZL40250LDF1
ZL40251LDG1
ZL40251LDF1
ZL40252LDG1
ZL40252LDF1
ZL40253LDG1
ZL40253LDF1
Ordering Information
ext. EEPROM
ext. EEPROM
int. EEPROM
int. EEPROM
ext. EEPROM
ext. EEPROM
int. EEPROM
int. EEPROM
6 Outputs
6 Outputs
6 Outputs
6 Outputs
10 Outputs
10 Outputs
10 Outputs
10 Outputs
Trays
Tape and Reel
Trays
Tape and Reel
Trays
Tape and Reel
Trays
Tape and Reel
Matte Tin
Package size: 8 x 8 mm, 56 Pin QFN
-40
C to +85
C
•
General Features
•
Automatic self-configuration at power-up from
external (ZL40250 or 2) or internal (ZL40251 or 3)
EEPROM; up to 8 configurations pin-selectable
•
PCIe 1, 2, 3, 4 compliant
•
Four multi-purpose I/O pins
•
SPI or I
2
C processor Interface
•
Core supply voltage options: 2.5V only, 3.3V
only, 1.8V+2.5V or 1.8V+3.3V
•
Space-saving 8x8mm QFN56 (0.5mm pitch)
•
Easy-to-use evaluation/programming software
Applications
Clock signal fanout, format conversion, frequency
division and skew adjustment in a wide variety of
equipment types
IC1P, IC1N
IC2P, IC2N
IC3P
XA
XB
DIV
DIV
DIV
xtal
driver
DIV
Path 1
DIV1
DIV2
VDDOA
OC1P, OC1N
OC2P, OC2N
VDDOB
OC3P, OC3N
VDDOC
OC4P, OC4N
OC5P, OC5N
VDDOD
OC6P, OC6N
OC7P, OC7N
VDDOE
OC8P, OC8N
VDDOF
OC9P, OC9N
OC10P, OC10N
Path 2
DIV3
DIV4
DIV5
RSTN
AC0/GPIO0
AC1/GPIO1
AC2/GPIO2
TEST/GPIO3
IF0/CSN
IF1/MISO
SCL/SCLK
SDA/MOSI
DIV6
10-output
devices only
(SPI or I2C Serial)
and GPIO Pins
Microprocessor
Port
DIV7
DIV8
DIV9
DIV10
Figure 1 - Functional Block Diagram
* some features require a higher-frequency input clock and enabling the output dividers
1
Microsemi Confidential
Copyright 2018. Microsemi Corporation. All Rights Reserved.
ZL40250-ZL40253
Data Sheet
Table of Contents
1.
2.
3.
4.
4.1
4.2
4.3
APPLICATION EXAMPLES .......................................................................................................... 4
PIN DIAGRAM ............................................................................................................................... 4
PIN DESCRIPTIONS ..................................................................................................................... 5
FUNCTIONAL DESCRIPTION ...................................................................................................... 7
D
EVICE
I
DENTIFICATION
................................................................................................................ 7
P
IN
-C
ONTROLLED
A
UTOMATIC
C
ONFIGURATION AT
R
ESET
............................................................. 7
ZL40250 and ZL40252—Internal ROM, External or No EEPROM ........................................................ 8
ZL40251 and ZL40253—Internal EEPROM .......................................................................................... 8
External Oscillator .................................................................................................................................. 9
External Crystal and On-Chip Driver Circuit .......................................................................................... 9
Ring Oscillator (for Auto-Configuration) ............................................................................................... 10
4.2.1
4.2.2
4.3.1
4.3.2
4.3.3
L
OCAL
O
SCILLATOR OR
C
RYSTAL
.................................................................................................. 9
4.4
4.5
4.6
I
NPUT
S
IGNAL
F
ORMAT
C
ONFIGURATION
...................................................................................... 10
P
ATH
1
AND
P
ATH
2 S
IGNAL
S
ELECTION
...................................................................................... 10
O
UTPUT
C
LOCK
C
ONFIGURATION
................................................................................................ 10
Output Enable, Signal Format, Voltage and Interfacing ...................................................................... 11
Output Frequency Configuration .......................................................................................................... 11
Output Duty Cycle Adjustment ............................................................................................................. 12
Output Phase Adjustment .................................................................................................................... 12
Output-to-Output Phase Alignment ...................................................................................................... 12
Output Clock Start and Stop ................................................................................................................ 13
SPI Slave ............................................................................................................................................. 14
SPI Master (ZL40250 and ZL40252 Only) ........................................................................................... 16
I
2
C Slave .............................................................................................................................................. 17
4.6.1
4.6.2
4.6.3
4.6.4
4.6.5
4.6.6
4.7
M
ICROPROCESSOR
I
NTERFACE
................................................................................................... 14
4.7.1
4.7.2
4.7.3
4.8 I
NTERRUPT
L
OGIC
...................................................................................................................... 19
4.9 R
ESET
L
OGIC
............................................................................................................................. 20
4.10
P
OWER
-S
UPPLY
C
ONSIDERATIONS
.......................................................................................... 20
4.11
A
UTO
-C
ONFIGURATION FROM
EEPROM
OR
ROM .................................................................... 20
4.11.1
4.11.2
4.11.3
Generating Device Configurations ....................................................................................................... 21
Direct EEPROM Write Mode (ZL40251 and ZL40253 Only) ............................................................... 21
Holding Other Devices in Reset During Auto-Configuration ................................................................ 21
4.12
4.13
5.
C
ONFIGURATION
S
EQUENCE
.................................................................................................... 21
P
OWER
S
UPPLY
D
ECOUPLING AND
L
AYOUT
R
ECOMMENDATIONS
............................................... 21
REGISTER DESCRIPTIONS ....................................................................................................... 21
5.1 R
EGISTER
T
YPES
....................................................................................................................... 21
5.1.1
5.1.2
5.1.3
Status Bits ............................................................................................................................................ 21
Configuration Fields ............................................................................................................................. 22
Bank-Switched Registers (ZL40251 and ZL40253 Only) .................................................................... 22
5.2
5.3
R
EGISTER
M
AP
.......................................................................................................................... 23
R
EGISTER
D
EFINITIONS
.............................................................................................................. 25
Global Configuration Registers ............................................................................................................ 25
Status Registers ................................................................................................................................... 32
Path 1 Configuration Registers ............................................................................................................ 38
Path 2 Configuration Registers ............................................................................................................ 39
Output Clock Configuration Registers .................................................................................................. 40
Input Clock Configuration Registers .................................................................................................... 45
5.3.1
5.3.2
5.3.3
5.3.4
5.3.5
5.3.6
6.
ELECTRICAL CHARACTERISTICS ........................................................................................... 47
2
Microsemi Confidential
ZL40250-ZL40253
7.
8.
9.
10.
Data Sheet
PACKAGE AND THERMAL INFORMATION .............................................................................. 57
MECHANICAL DRAWING .......................................................................................................... 58
ACRONYMS AND ABBREVIATIONS ......................................................................................... 59
DATA SHEET REVISION HISTORY ........................................................................................... 59
List of Figures
Figure 1 - Functional Block Diagram ........................................................................................................................... 1
Figure 2 - Application Examples: Ethernet and PCIe Clocks ...................................................................................... 4
Figure 3 - Pin Diagram ................................................................................................................................................. 4
Figure 4 - Crystal Equivalent Circuit / Recommended Crystal Circuit ......................................................................... 9
Figure 5 - SPI Read Transaction Functional Timing.................................................................................................. 15
Figure 6 - SPI Write Enable Transaction Functional Timing (ZL40251 and ZL40253 Only) ..................................... 15
Figure 7 - SPI Write Transaction Functional Timing .................................................................................................. 16
Figure 8 - I
2
C Read Transaction Functional Timing .................................................................................................. 18
Figure 9 - I
2
C Register Write Transaction Functional Timing .................................................................................... 18
Figure 10 - I
2
C EEPROM Write Transaction Functional Timing (ZL40251 and ZL40253 Only) ............................... 18
Figure 11 - I
2
C EEPROM Read Status Transaction Functional Timing (ZL40251 and ZL40253 Only) .................... 18
Figure 12 - Interrupt Structure ................................................................................................................................... 19
Figure 13 - Electrical Characteristics: Clock Inputs ................................................................................................... 49
Figure 14 - Example External Components for Differential Input Signals ................................................................. 50
Figure 15 - Electrical Characteristics: Differential Clock Outputs .............................................................................. 50
Figure 16 - Example External Components for Output Signals ................................................................................. 52
Figure 17 - SPI Slave Interface Timing ...................................................................................................................... 53
Figure 18 - SPI Master Interface Timing .................................................................................................................... 55
Figure 19 - I
2
C Slave Interface Timing ....................................................................................................................... 56
List of Tables
Table 1 - Pin Descriptions ............................................................................................................................................ 5
Table 2 - Crystal Selection Parameters ..................................................................................................................... 10
Table 3 - SPI Commands .......................................................................................................................................... 14
Table 4 - Register Map .............................................................................................................................................. 23
Table 5 - Recommended DC Operating Conditions .................................................................................................. 47
Table 6 - Electrical Characteristics: Supply Currents ................................................................................................ 47
Table 7 - Electrical Characteristics: Non-Clock CMOS Pins ..................................................................................... 48
Table 8 - Electrical Characteristics: XA Clock Input .................................................................................................. 49
Table 9 - Electrical Characteristics: Clock Inputs, ICxP/N ......................................................................................... 49
Table 10 - Electrical Characteristics: LVDS Clock Outputs ....................................................................................... 50
Table 11 - Electrical Characteristics: LVPECL Clock Outputs .................................................................................. 51
Table 12 - Electrical Characteristics: HCSL Clock Outputs ....................................................................................... 51
Table 13 - Electrical Characteristics: CMOS and HSTL (Class I) Clock Outputs ...................................................... 51
Table 14 - Electrical Characteristics: Jitter and Skew Specifications ........................................................................ 52
Table 15 - Electrical Characteristics: SPI Slave Interface Timing, Device Registers ................................................ 53
Table 16 - Electrical Characteristics: SPI Slave Interface Timing, Internal EEPROM .............................................. 54
Table 17 - Electrical Characteristics: SPI Master Interface Timing (ZL40250 and ZL40252 Only) ........................... 55
Table 18 - Electrical Characteristics: I
2
C Slave Interface Timing .............................................................................. 56
Table 19 - 8x8mm QFN Package Thermal Properties .............................................................................................. 57
3
Microsemi Confidential
ZL40250-ZL40253
1. Application Examples
Application Example 1:
7
625MHz
from other
timing IC
7x 156.25MHz differential
2x 125MHz differential
2x 25MHz 1.8V CMOS
100MHz
Data Sheet
Application Example 2:
8
8x 100MHz differential (HCSL)
1x 100MHz differential (LVDS)
2x 50MHz 2.5V CMOS
ZL40253
2
ZL40253
Figure 2 - Application Examples: Ethernet and PCIe Clocks
2. Pin Diagram
The device is packaged in a 8x8mm 56-pin QFN.
VDDOC
VDDOD
VDDOE
43
42
41
40
39
38
37
36
35
34
33
32
31
GND (E-pad)
30
29
15
16
17
18
19
20
21
22
23
24
25
26
27
28
OC4N
OC5N
OC6N
56
55
54
53
52
51
50
49
48
47
46
45
44
VDDOB
OC3P
OC3N
VDDL
OC2N
OC2P
VDDOA
OC1P
OC1N
VDDL
VDDH
XA
XB
VDDL
OC7N
OC4P
OC5P
OC6P
OC7P
VDDL
VDDL
VDDL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
VDDH
OC8P
OC8N
VDDL
OC9N
OC9P
VDDOF
OC10P
OC10N
VDDL
VDDH
VDDL
VDDIO
RSTN
SDA/MOSI
SCL/SCLK
IF1/MISO
IC1P
IC2P
IC3P
AC1/GPIO1
AC0/GPIO0
IF0/CSN
Figure 3 - Pin Diagram
TEST/GPIO3
4
Microsemi Confidential
AC2/GPIO2
IC1N
VDDH
IC2N
ZL40250-ZL40253
3. Pin Descriptions
Data Sheet
All device inputs and outputs are LVCMOS unless described otherwise. The Type column uses the following
symbols: I – input, O – output, A – analog, P – power supply pin. All GPIO and SPI/I
2
C interface pins have Schmitt-
trigger inputs and have output drivers that can be disabled (high impedance).
Table 1 - Pin Descriptions
Pin #
Name
Type
Description
Input Clock Pins
Differential or Single-ended signal format. Programmable frequency.
Differential:
See
Table 9
for electrical specifications, and see
Figure 14
for
recommended external circuitry for interfacing these differential inputs to
LVDS, LVPECL, CML or HSCL output pins on neighboring devices.
Single-ended:
For input signal amplitude >2.5V, connect the signal directly to
ICxP pin. For input signal amplitude ≤2.5V, AC-coupling the signal to ICxP
is recommended. Connect the N pin to a capacitor (0.1F or 0.01F) to
VSS. As shown in
Figure 14
, the ICxP and ICxN pins are internally biased
to approximately 1.3V. Treat the ICxN pin as a sensitive node; minimize
stubs; do not connect to anything else including other ICxN pins.
Unused:
Set
ICEN.ICxEN=0.
The ICxP and ICxN pins can be left floating.
Note that the IC3N pin is not bonded out. A differential signal can be
connected to IC3P by AC-coupling the POS trace to IC3P and terminating
the signal on the driver side of the coupling cap.
Crystal or Input Clock Pins
Crystal:
MCR2.XAB=01. An on-chip crystal driver circuit is designed to work
with an external crystal connected to the XA and XB pins. See section
4.3.2
for crystal characteristics and recommended external components.
Input Clock:
MCR2.XAB=10. An external local oscillator or clock signal can be
connected to the XA pin. The XB pin must be left unconnected. The signal
on XA can be as large as 3.3V even when VDDH is only 2.5V.
Output Clock Pins
LVDS, programmable differential (which includes LVPECL), HCSL, HSTL or
1 or 2 CMOS. Programmable frequency. Programmable VCM and VOD in
programmable differential mode. Programmable drive strength in CMOS
and HSTL modes. See
Figure 16
for example external interface circuitry.
See
Table 10, Table 11
and
Table 12
for electrical specifications for LVDS,
LVPECL and HCSL, respectively.
See
Table 13
for electrical specifications for interfacing to CMOS and HSTL
inputs on neighboring devices.
Outputs OC2, OC5, OC7 and OC10 are not present on 6-output products.
Reset (Active Low)
When this global asynchronous reset is pulled low, all internal circuitry is reset
to default values. The device is held in reset as long as RSTN is low.
Minimum low time is 1µs.
Auto-Configure [2:0] / General Purpose I/O 0, 1 and 2
Auto Configure:
On the rising edge of RSTN these pins behave as AC[2:0]
and specify one of the configurations stored in ROM or EEPROM. See
section
4.2.
15, 16
18, 19
20
IC1P, IC1N
IC2P, IC2N
IC3P
I
I
I
12
13
XA
XB
A/I
8, 9
6, 5
2, 3
55, 56
53, 52
47, 48
45, 44
41, 40
37, 38
35, 34
OC1P, OC1N
OC2P, OC2N
OC3P, OC3N
OC4P, OC4N
OC5P, OC5N
OC6P, OC6N
OC7P, OC7N
OC8P, OC8N
OC9P, OC9N
OC10P, OC10N
O
29
RSTN
I
23
22
28
AC0/GPIO0
AC1/GPIO1
AC2/GPIO2
I/O
5
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