PI6C21200
1:12 Clock Driver for Intel PCI-Express Chipsets
Features
• Twelve Pairs of PCI-Express Differential Clocks (HCSL
compatible signaling)
• Low skew < 50ps
• Low jitter < 50ps
• Output Enable for all outputs
• Outputs tristate control via SMBus
• Power Management Control
• Programmable PLL Bandwidth
• PLL or Fan out operation
• Gear Ratio supporting different output frequencies
• 3.3V Operation
• 56-pin Packages (Pb-Free & Green):
- TSSOP (A56) and SSOP (V56)
Description
PI6C21200 is a high-speed, low-noise PCI-Express differential
clock buffer designed to be a companion with PI6C410B clock
synthesizer. The device distributes twelve copies of the
differential SRC clock coming from PI6C410B. The output
frequency can be ratioed to offer a derivative frequency from
the input frequency. Each differential output is controlled by
individual OE pin, except OUT10 and OUT11 are sharing one
OE_10#_11# pin. The clock outputs are controlled by input selec-
tion of SA_0, SA_1, SA_2 via SMBus, SCLK and SDA.
Block Diagram
OE [0:10]#
VTT_PWRGD#
/ PWRDWN
SCLK
SDA
SA_[0:1]
SA_2 /
PLLBypress#
SRC
SCR#
Pinout Diagram
Output
Control
HIGH_BW#
SRC_IN
SRC_IN#
SA_0
OE_0#
OUT0
OUT0#
OE_1#
OUT1
OUT1#
VDD
VSS
OUT2
OUT2#
OE_2#
OUT3
OUT3#
OE_3#
OUT4
OUT4#
OE_4#
VDD
VSS
OUT5
OUT5#
OE_5#
SA_1
SDA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
VDD_A
VSS_A
IREF
OE_10#_11#
OUT11
OUT11#
VDD
VSS
OUT10
OUT10#
FS_A
VTT_PWRGD# / PWRDWN
OE_9#
OUT9
OUT9#
OE_8#
OUT8
OUT8#
VDD
VSS
OUT7
OUT7#
OE_7#
OUT6
OUT6#
OE_6#
SA_2 /PLLBypass#
SCL
OUT0
OUT0#
OUT1
OUT1#
OUT2
OUT2#
OUT3
OUT3#
OUT4
OUT4#
OUT5
OUT5#
OUT6
OUT6#
SMBus
Controller
HIGH_BW#
PLL
OUT7
OUT7#
OUT8
OUT8#
OUT9
OUT9#
OUT10
OUT10#
OUT11
OUT11#
1
PS8820
02/28/06
PI6C21200
1:12 Clock Driver for Intel
PCI-Express Chipsets
Pin Descriptions
Pin Name
PLL_BW#
SRC & SRC#
OUT[0:9] &
OUT[0:9]#
OUT[10:11] &
OUT[10:11]#
OE_[0:9]#
OE_10#_11#
SA_[0:1]
SA_2 / PLL-
BYPASS#
SCLK
SDA
I
REF
FS_A
VTT_PWRGD#
/ PWRDWN
V
DD
V
SS
V
SS_A
V
DD_A
Type
Input
Input
Output
Output
Input
Input
Input
Input
Input
I/O
Input
Input
Input
Power
Ground
Ground
Power
Pin Number
1
2, 3
6, 7, 9, 10, 13, 14, 16,
17, 19, 20, 24, 25, 32, 33,
35, 36, 39, 40, 42, 43
47, 48, 51, 52
5, 8, 15, 18, 21, 26, 31,
34, 41, 44
53
4, 27
30
29
28
54
46
45
11, 22, 38, 50
12, 23, 37, 49
55
56
Descriptions
3.3V LVTTL input for selecting the PLL bandwidth. (High = Low BW)
0.7V Differential SRC input from PI6C410B clock synthesizer
0.7V Differential outputs, geared to the ratio of input clock. Can be
configured to be 1:1 ratio.
0.7V Differential outputs, geared to the ratio of input clock same as
OUT[0:9]. Can be configured to be 1:1 ratio.
3.3V LVTTL input for enabling outputs, active low. Control each
OUT[0:9] pair.
3.3V LVTTL input for enabling outputs, active low. Control each
OUT[10:11] pair.
3.3V LVTTL input for selecting the SMBus address
3.3V LVTTL input for selecting fan-out of PLL operation, and SMBus
address. 0 = PLL Bypass, 1 = PLL mode
SMBus compatible SCLOCK input
SMBus compatible SDATA
External resistor connection to set the differential output current
3.3V LVTTL inputs for CPU frequency selection
0 = above 200 MHz, 1 = below 200 MHz
3.3V LVTTL input for Power Down operation, active high
3.3V Power Supply for Outputs
Ground for Outputs
Ground for PLL
3.3V Power Supply for PLL
Serial Data Interface (SMBus)
PI6C21200 is a slave only SMBus device that supports random byte read and write indexed block read and write protocol using a
single 7-bit address and read/write bit as shown below.
SMBus Address Selection by SA_[0:2]
SA_2/
PLLBypass#
0
0
0
0
1
1
1
1
SA_1
0
0
1
1
0
0
1
1
SA_0
0
1
0
1
0
1
0
1
SMBus
Address
D0
D2
D4
D6
D8
DA
DC
DE
PLL
Mode
Bypass
Bypass
Bypass
Bypass
PLL
PLL
PLL
PLL
2
PS8820
02/28/06
PI6C21200
1:12 Clock Driver for Intel
PCI-Express Chipsets
Indexed Block Read and Write Protocol
Block Write Protocol
Bit
1
2:8
9
10
11:18
19
20:27
28
29:36
37
38:45
46
....
....
....
....
Start
Slave address - 7 bits
Write = 0
Acknowledge from slave
Command Code - 8 Bits
'00000000' Stand for block operation
Acknowledge from slave
Byte Count from master - 8 bits
Acknowledge from slave
Datat byte 0 from master - 8 bits
Acknowledge from slave
Datat byte 1 from master - 8 bits
Acknowledge from slave
Data bytes from master/Acknowledge
Data byte N - 8 bits
Acknowledge from slave
Stop
Description
Bit
1
2:8
9
10
11:18
19
20
21:27
28
29
30:37
38
39:46
47
48:55
56
....
....
....
....
Start
Slave address - 7 bits
Write = 0
Acknowledge from slave
Command Code - 8 Bits
'00000000' Stand for block operation
Acknowledge from slave
Repeat start
Slave address - 7 bits
Read = 1
Acknowledge from slave
Byte count from slave - 8 bits
Acknowledge from host
Data byte 0 from slave - 8 bits
Acknowledge from host
Data byte 1 from slave - 8 bits
Acknowledge from host
Data bytes from slave/Acknowledge
Data byte N from slave - 8 bits
Acknowledge from host - 38 bits
Stop
Block Read Protocol
Description
3
PS8820
02/28/06
PI6C21200
1:12 Clock Driver for Intel
PCI-Express Chipsets
Random Byte Read and Write Protocol
Byte Write Protocol
Bit
1
2:8
9
10
11:18
19
20:27
28
29
Start
Slave address - 7 bits
Write = 0
Acknowledge from slave
Command Code - 8 bits
'100xxxxx' stands for byte operation, bits[6:0]
of the command code represents the offset of
the byte to be accessed.
Acknowledge from slave
Data byte from master - 8 bits
Acknowledge from slave
Stop
Description
Bit
1
2:8
9
10
11:18
19
20:27
21:27
28
29
30:37
38
39
Start
Slave address - 7 bits
Write - 0
Acknowledge from slave
Command Code - 8 bits
'100xxxxx' stands for byte operation, bits[6:0]
of the command code represents the offset of the
byte to be accessed.
Acknowledge from slave
Repeat start
Slave address - 7 bits
Read = 1
Acknowledge from slave
Data byte from slave - 8 bits
Acknowledge from master - 38 bits
Stop
Byte Read Protocol
Description
4
PS8820
02/28/06
PI6C21200
1:12 Clock Driver for Intel
PCI-Express Chipsets
Data Byte 0: Control Register
Bit
0
1
2
3
4
5
6
7
Descriptions
FSB Gear Ratio SMBus
FSB Gear Ratio SMBus
FSB Gear Ratio SMBus
FSB Gear Ratio SMBus
FS_A PI6C410B latched input
Reserved
Group of 2 gear ratio select
1 = 1:1, 0 = Gear Raito
Group of 10 gear ratio select
1 = 1:1, 0 = Gear Raito
Type
RW
RW
RW
RW
RW
RW
RW
RW
Power Up Condition
1
Depends on FS_A pin
(1)
0
Depends on FS_A pin
(1)
Latch
1
1
1
OUT[10:11],
OUT[10:11]#
OUT[0:9],
OUT[0:9]#
Output(s) Affected
Note:
1. When FS_A = 1, Bit 1 = 0 and Bit 3 = 1; When FS_A = 0, Bit 1 = 1 and Bit 3 = 0
Data Byte 1: Control Register
Bit
0
1
2
3
4
5
6
7
OUTPUTS enable
1 = Enabled
0 = Hi-Z
Descriptions
Type
RW
RW
RW
RW
RW
RW
RW
RW
Power Up Condition
1 = Enabled
1 = Enabled
1 = Enabled
1 = Enabled
1 = Enabled
1 = Enabled
1 = Enabled
1 = Enabled
Output(s) Affected
OUT0, OUT0#
OUT1, OUT1#
OUT2, OUT2#
OUT3, OUT3#
OUT4, OUT4#
OUT5, OUT5#
OUT6, OUT6#
OUT7, OUT7#
Data Byte 2: Control Register
Bit
0
1
2
3
4
5
6
Descriptions
OUTPUTS enable
1 = Enabled
0 = Hi-Z
Reserved
PLL/BYPASS#
0 = Fanout,1 = PLL
PLL Bandwidth
0 = High Bandwidth,
1 = Low Bandwidth
Outputs current select at PWRDWN = 1
1 = 2 x I
REF
,
0 = HiZ
Type
RW
RW
RW
RW
RW
RW
RW
1 = PLL
1 = Low
OUT[0:11], OUT[0:11]#
OUT[0:11], OUT[0:11]#
Power Up Condition
1 = Enabled
1 = Enabled
1 = Enabled
1 = Enabled
Output(s) Affected
OUT8, OUT8#
OUT9, OUT9#
OUT10, OUT10#
OUT11, OUT11#
7
RW
1
5
PS8820
02/28/06
Embedded System
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