PI6C410
Clock Generator for Intel PCI-Express Desktop Chipset
Product Features
• 14.318 MHz Crystal Input
• Selectable of 100, 133, 166, 200, 266, 333, and 400MHz CPU
Output Frequencies
• SMBus: Power Management Control
• Spread Spectrum support (-0.5% down spread)
• Packaging (Pb-free & Green available):
-56-Pin SSOP (V)
-56-Pin TSSOP (A)
Product Description
PI6C410 is a high-speed, low-noise clock generator designed to
work with Intel Desktop PCI-Express Chipset.
Spread Spectrum PLL based clock generator reduce EMI emis-
sion and support a wide range of frequencies.
Jitter Performance
• < 85ps Cycle to Cycle CPU clock jitter
• < 350ps Cycle to Cycle 48MHz clock jitter
• < 500ps Cycle to Cycle PCI clock jitter
• < 125ps Cycle to Cycle SRC clock jitter
• < 1000ps Cycle to Cycle REF clock jitter
Skew Performance
• < 100ps Output to output CPU clock skew
• < 500ps Output to output PCI clock skew
• < 250ps Output to output SRC clock skew
Output Features
• Two Pairs of Differential CPU Clocks
• One selectable of CPU/SRC Clock
• Six Pairs of SRC Clocks
• Nine PCI Clocks
• One 48 MHz USB clock
• One REF clock
• One 96 MHz Differential clock
Logic Block Diagram
XTAL_IN
XTAL_OUT
XTAL
OSC
PLL 2
/2
PLL 1
SDA
SCL
Div
DOT_96
DOT 96#
USB_48
REF
PCI [0:5]
PCIF[0:2]
Pin Description
VDD_PCI
VSS_PCI
PCI_3
PCI_4
PCI_5
VSS_PCI
VDD_PCI
PCIF_0 / ITP_EN
PCIF_1
PCIF_2
VDD_48
USB_48
VSS_48
DOT_96
DOT_96#
FS_B / TEST_MODE
VTT_PWRGD# / PWRDWN
FS_A
SRC_1
SRC_1#
VDD_SRC
SRC_2
SRC_2#
SRC_3
SRC_3#
SRC_4
SRC_4#
VDD_SRC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
PCI_2
PCI_1
PCI_0
FS_C / TEST_SEL
REF
VSS_REF
XTAL_IN
XTAL_OUT
VDD_REF
SDA
SCL
VSS_CPU
CPU_0
CPU_0#
VDD_CPU
CPU_1
CPU_1#
IREF
VSS_A
VDD_A
CPU2_ITP / SRC7
CPU2_ITP# / SRC7#
VDD_SRC
SRC_6
SRC_6#
SRC_5
SRC_5#
VSS_SRC
SMBus
Logic
Div
FS_A
FS_B / TEST_MODE
FS_C / TEST_SEL
VTT_PWRGD#
/ PWRDWN
PCIF_0 / ITP_EN
C
O
N
T
R
O
L
SRC [1:6]
SRC [1:6]#
CPU2_ITP / SRC7
CPU2_ITP# / SRC7#
Div
CPU[0:1]
CPU[0:1]#
1
PS8734A
09/02/04
PI6C410
Clock Generator for Intel
PCI-Express Desktop Chipset
Pin Description
Pin Name
REF
XTAL_IN
XTAL_OUT
CPU[0:1] & CPU[0:1]#
SRC[1:6] & SRC[1:6]#
CPU2_ITP / SRC_7 &
CPU2_ITP# / SRC_7#
PCIF_0 / ITP_EN
PCIF[1:2]
PCI[0:5]
USB_48
DOT_96 & DOT_96#
FS_A
FS_B / TEST_MODE
FS_C / TEST_SEL
IREF
VTT_PWRGD# /
PWRDWN
SDA
SCL
VDD_PCI
VDD_48
VDD_SRC
VDD_CPU
VDD_REF
VSS_PCI
VSS_48
VSS_SRC
VSS_CPU
VSS_REF
VDD_A
VSS_A
Type
Output
Input
Output
Output
Output
Pin No
52
50
49
40, 41, 43, 44
19, 20, 22, 23,
24, 25, 26, 27,
30, 31, 32, 33
35, 36
8
9, 10
3, 4, 5, 54, 55,
56
12
14, 15
18
16
53
39
17
47
46
1, 7
11
21, 28, 34
42
48
2, 6
13
29
45
51
37
38
Descriptions
3.3V 14.31818MHz output
14.31818MHz crystal input
14.31818MHz crystal output
Differential CPU outputs
Differential Serial Reference Clock outputs
Selectable Differential CPU or SRC clock output
ITP_EN = 0 @ Vtt_Pwrgd# assertion = SRC
ITP_EN = 1 @ Vtt_Pwrgd# assertion = CPU
33MHz clock output / CPU2 select when HIGH
33MHz clocks outputs (free running)
33MHz clocks outputs
48MHz clock output
96MHz differential clock output
3.3V LVTTL inputs for CPU frequency selection
3.3V LVTTL inputs for CPU frequency selection / Test Mode
select: 0 = HiZ, 1 = Ref/N
3.3V LVTTL inputs for CPU frequency selection / Test Mode
select if pulled to 3.3V when Vtt_Pwrgd# is asserted LOW
External resistor connection for internal current reference
3.3V LVTTL Level sensitive strobe used to determine to latch
the FS_A, FS_B/TEST_MODE, FS_C/TEST_SEL and PCIF0/
ITP_EN inputs (active low) / 3.3V LVTTL active high input for
Power Down operation.
SMBus compatible SDATA
SMBus compatible SCLOCK
3.3V Power Supply for Outputs
3.3V Power Supply for Outputs
3.3V Power Supply for Outputs
3.3V Power Supply for Outputs
3.3V Power Supply for Outputs
Ground for Outputs
Ground for Outputs
Ground for Outputs
Ground for Outputs
Ground for Outputs
3.3V Power Supply for PLL
Ground for PLL
Output
Input / Output
Output
Output
Output
Output
Input
Input
Input
Input
Input
I/O
Input
Power
Power
Power
Power
Power
Ground
Ground
Ground
Ground
Ground
Power
Ground
2
PS8734A
09/02/04
PI6C410
Clock Generator for Intel
PCI-Express Desktop Chipset
Functionality
Frequency Selection
FS_C
1
0
0
0
0
1
1
1
FS_B
0
0
1
1
0
0
1
1
FS_A
1
1
1
0
0
0
0
1
CPU
100MHz
133MHz
166MHz
200MHz
266MHz
333MHz
400MHz
Reserved
SRC
100MHz
100MHz
100MHz
100MHz
100MHz
100MHz
100MHz
100MHz
PCIF / PCI
33MHz
33MHz
33MHz
33MHz
33MHz
33MHz
33MHz
33MHz
REF
14.318MHz
14.318MHz
14.318MHz
14.318MHz
14.318MHz
14.318MHz
14.318MHz
14.318MHz
DOT_96
96MHz
96MHz
96MHz
96MHz
96MHz
96MHz
96MHz
96MHz
USB_48
48MHz
48MHz
48MHz
48MHz
48MHz
48MHz
48MHz
48MHz
Note
1
1
1
1
1
1
1
1
Notes:
1. Refer to DC Electrical Characteristics for FS_A, FS_B and FS_C (Vih_FS, Vil_FS) threshold levels
Test Mode Selection
TEST_MODE
1
0
CPU
REF/N
Hi-Z
SRC
REF/N
Hi-Z
PCIF / PCI
REF/N
Hi-Z
REF
REF
Hi-Z
DOT_96
REF/N
Hi-Z
USB_48
REF/N
Hi-Z
Note
2
2
Notes:
2. Test mode will occur where the SMBus Bit 6 of Byte 6 = 1, or FS_C/TEST_SEL is set to logic high level.
PWRDWN Functionality
PWRDWN
0
1
CPU
Normal
Iref
×
2 or
Float
CPU#
Normal
Float
SRC
Normal
Iref
×
2 or
Float
SRC#
Normal
Float
PCIF /
PCI
33MHz
Low
REF
14.318MHz
Low
DOT_96
Normal
Iref
×
2 or
Float
DOT_96#
Normal
Float
USB_48
48MHz
Low
3
PS8734A
09/02/04
PI6C410
Clock Generator for Intel
PCI-Express Desktop Chipset
Serial Data Interface (SMBus)
PI6C410 is a slave only SMBus device that supports indexed block read and indexed block write protocol using a single 7-bit ad-
dress and read/write bit as shown below.
Address Assignment
A6
1
A5
1
A4
0
A3
1
A2
0
A1
0
A0
1
R/W
1/0
Data Protocol
1 bit
Start
bit
7 bits
Slave Addr
1
R/W
1
Ack
8 bits
Register
offset
1
Ack
8 bits
Byte
Count
=N
1
Ack
8 bits
Data
Byte 0
1
Ack
…
8 bits
Data
Byte N
-1
1
Ack
1 bit
Stop
bit
Notes:
1. Register offset for indicating the starting register for indexed block write and indexed block read. Byte Count in write mode cannot be 0.
Data Byte 0: Control Register
Bit
0
1
2
3
4
5
6
7
Reserved
SRC_1 Output Enable
1 = Enabled, 0 = Disabled (Hi-Z)
SRC_2 Output Enable
1 = Enabled, 0 = Disabled (Hi-Z)
SRC_3 Output Enable
1 = Enabled, 0 = Disabled (Hi-Z)
SRC_4 Output Enable
1 = Enabled, 0 = Disabled (Hi-Z)
SRC_5 Output Enable
1 = Enabled, 0 = Disabled (Hi-Z)
SRC_6 Output Enable
1 = Enabled, 0 = Disabled (Hi-Z)
CPU_2 / SRC_7 Output Enable
1 = Enabled, 0 = Disabled (Hi-Z)
Descriptions
Type
RW
RW
RW
RW
RW
RW
RW
RW
1 = Enabled
1 = Enabled
1 = Enabled
1 = Enabled
1 = Enabled
1 = Enabled
1 = Enabled
SRC_1
SRC_2
SRC_3
SRC_4
SRC_5
SRC_6
CPU_2 / SRC_7
19, 20
22, 23
24, 25
26, 27
30, 31
32, 33
35, 36
NA
NA
NA
NA
NA
NA
NA
Power Up
Condition
Output(s) Affected
Pin
Source Pin
4
PS8734A
09/02/04
PI6C410
Clock Generator for Intel
PCI-Express Desktop Chipset
Data Byte 1: Control Register
Bit
Descriptions
Type
Power Up
Condition
Output(s) Affected
Pin
3, 4, 5, 8, 9, 10,
19, 20, 22, 23,
24, 25, 26, 27,
30, 31, 32, 33,
35, 36, 40, 41,
43, 44, 54, 55,
56
43, 44
40, 41
Source Pin
0
Spread Spectrum
1 = On, 0 = Off
RW
0 = Spread off
CPU[0:2], SRC[1:7],
PCI[0:5], PCIF[0:2]
NA
1
2
3
4
5
6
7
CPU_0 output enable
1 = Enabled, 0 = Disabled (Hi-Z)
CPU_1 output enable
1 = Enabled, 0 = Disabled (Hi-Z)
Reserved
REF Output Enable
1 = Enabled, 0 = Disabled
USB_48 Output Enable
1 = Enabled, 0 = Disabled
DOT_96 Output Enable
1 = Enabled, 0 = Disabled (Hi-Z)
PCIF_0 Output Enable
1 = Enabled, 0 = Disabled
RW
RW
RW
RW
RW
RW
RW
1 = Enabled
1 = Enabled
CPU_0, CPU_0#
CPU_1, CPU_1#
NA
NA
1 = Enabled
1 = Enabled
1 = Enabled
1 = Enabled
REF
USB_48
DOT_96 & DOT96#
PCIF_0
52
12
14, 15
8
NA
NA
NA
NA
Data Byte 2: Control Register
Bit
0
1
2
3
4
5
6
7
Descriptions
PCIF_1 Output Enable
1 = Enabled, 0 = Disabled
PCIF_2 Output Enable
1 = Enabled, 0 = Disabled
PCI_0 Output Enable
1 = Enabled, 0 = Disabled
PCI_1 Output Enable
1 = Enabled, 0 = Disabled
PCI _2 Output Enable
1 = Enabled, 0 = Disabled
PCI _3 Output Enable
1 = Enabled, 0 = Disabled
PCI _4 Output Enable
1 = Enabled, 0 = Disabled
PCI _5 Output Enable
1 = Enabled, 0 = Disabled
Type
RW
RW
RW
RW
RW
RW
RW
RW
Power Up
Condition
1 = Enabled
1 = Enabled
1 = Enabled
1 = Enabled
1 = Enabled
1 = Enabled
1 = Enabled
1 = Enabled
Output(s) Affected
PCIF_1
PCIF_2
PCI_0
PCI_1
PCI_2
PCI_3
PCI_4
PCI_5
Pin
9
10
54
55
56
3
4
5
Source Pin
NA
NA
NA
NA
NA
NA
NA
NA
5
PS8734A
09/02/04
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