Write Enable (WE) inputs LOW. Data on the eight I/O pins (I/O
0
through I/O
7
) is then written into the location specified on the
address pins (A
0
through A
18
).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the I/O pins.
The eight input/output pins (I/O
0
through I/O
7
) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW, and WE LOW).
The WCFS4008V1C is available in standard 400-mil-wide
36-pin SOJ package and 44-pin TSOP II package with center
power and ground pinout.
Functional Description
The WCFS4008V1C is a high-performance CMOS Static RAM
organized as 524K words by 8 bits. Easy memory expansion
is provided by an active LOW Chip Enable (CE), an active
LOW Output Enable (OE), and three-state drivers. Writing to
the device is accomplished by taking Chip Enable (CE) and
Logic Block Diagram
Pin Configuration
SOJ
Top View
TSOP II
Top View
NC
A
18
A
17
A
16
A
15
OE
I/O
7
I/O
6
GND
V
CC
I/O
5
I/O
4
A
14
A
13
A
12
A
11
A
10
NC
I/O
0
INPUT BUFFER
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
A
10
I/O
1
ROW DECODER
I/O
2
SENSE AMPS
512K x 8
ARRAY
I/O
3
I/O
4
I/O
5
CE
WE
OE
COLUMN
DECODER
POWER
DOWN
I/O
6
I/O
7
A
0
A
1
A
2
A
3
A
4
CE
I/O
0
I/O
1
V
CC
GND
I/O
2
I/O3
WE
A
5
A
6
A
7
A
8
A
9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
NC
NC
A
0
A
1
A
2
A
3
A
4
CE
I/O
0
I/O
1
V
CC
V
SS
I/O
2
I/O
3
WE
A
5
A
6
A
7
A
8
A
9
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
NC
NC
NC
A
18
A
17
A
16
A
15
OE
I/O
7
I/O
6
V
SS
V
CC
I/O
5
I/O
4
A
14
A
13
A
12
A
11
A
10
NC
NC
NC
Selection Guide
WCFS4008V1C 12ns
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum CMOS Standby Current (mA)
Comm’l
Comm’l
12
85
10
A
11
A
12
A
13
A
14
A
15
A
16
A
17
A
18
WCFS4008V1C
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................–65×C to +150×C
Ambient Temperature with
Power Applied............................................–55×C to +125×C
Supply Voltage on V
CC
to Relative GND
[1]
.... –0.5V to +4.6V
DC Voltage Applied to Outputs
in High Z State
[1]
....................................–0.5V to V
CC
+ 0.5V
Range
Commercial
Ambient
Temperature
0°C to +70°C
V
CC
3.3V
±
0.3V
DC Input Voltage
[1]
................................ –0.5V to V
CC
+ 0.5V
Current into Outputs (LOW) ........................................ 20 mA
Operating Range
Electrical Characteristics
Over the Operating Range
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
I
SB1
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
[1]
Input Load Current
Output Leakage
Current
V
CC
Operating
Supply Current
Automatic CE
Power-Down Current
—TTL Inputs
Automatic CE
Power-Down Current
—CMOS Inputs
GND < V
I
< V
CC
GND < V
OUT
< V
CC
,
Output Disabled
V
CC
= Max.,
f = f
MAX
= 1/t
RC
Max. V
CC
, CE > V
IH
V
IN
> V
IH
or
V
IN
< V
IL
, f = f
MAX
Max. V
CC
,
CE > V
CC
– 0.3V,
V
IN
> V
CC
– 0.3V,
or V
IN
< 0.3V, f = 0
Comm’ll
Comm’l
Test Conditions
V
CC
= Min.,
I
OH
= –4.0 mA
V
CC
= Min.,
I
OL
= 8.0 mA
2.0
–0.3
–1
–1
WCFS4008V1C 12ns
Min.
2.4
0.4
V
CC
+ 0.3
0.8
+1
+1
85
40
Max.
Unit
V
V
V
V
µA
µA
mA
mA
I
SB2
10
mA
Capacitance
[2]
Parameter
C
IN
C
OUT
Description
Input Capacitance
I/O Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz,
V
CC
= 3.3V
Max.
8
8
Unit
pF
pF
Note:
1. V
IL
(min.) = –2.0V for pulse durations of less than 20 ns
2. Tested initially and after any design or process changes that may affect these parameters.
2
WCFS4008V1C
AC Test Loads and Waveforms
3.3V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
(a)
R2
351
Ω
R1 317
Ω
50
Ω
OUTPUT
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
Z
0
=50
Ω
30pF*
V
TH
= 1.5V
(b)
ALL INPUT PULSES
3.3V
90%
GND
Rise time > 1 V/ns
10%
90%
10%
Fall time:
> 1 V/ns
(c)
3
WCFS4008V1C
AC Switching Characteristics
[3]
Over the Operating Range
WCFS4008V1C 12ns
Parameter
READ CYCLE
t
power[4]
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
WRITE CYCLE
[7, 8]
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z
[6]
WE LOW to High Z
[5, 6]
12
8
8
0
0
8
6
0
3
6
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
V
CC
(typical) to the first access
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z
[5, 6]
CE LOW to Low Z
[6]
CE HIGH to High Z
[5, 6]
CE LOW to Power-Up
CE HIGH to Power-Down
0
12
3
6
0
6
3
12
6
1
12
12
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
Min.
Max.
Unit
Notes:
3. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V.
4. t
POWER
gives the minimum amount of time that the power supply should be at stable, typical Vcc values until the first memory access can be performed.
5. t
HZOE
, t
HZCE
, and t
HZWE
are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured
±
500 mV from steady-state voltage.
6. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
7. The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of
these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
8. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of t
HZWE
and t
SD
.
4
WCFS4008V1C
Switching Waveforms
Read Cycle No. 1
[9, 10]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE Controlled)
[10, 11]
ADDRESS
t
RC
CE
t
ACE
OE
t
DOE
t
LZOE
HIGH IMPEDANCE
t
LZCE
V
CC
SUPPLY
CURRENT
t
PU
50%
t
HZOE
t
HZCE
DATA VALID
t
PD
50%
I
SB
I
CC
HIGH
IMPEDANCE
DATA OUT
Notes:
9. Device is continuously selected. OE, CE = V
IL
.
10. WE is HIGH for read cycle.
11. Address valid prior to or coincident with CE transition LOW.
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