For full common-mode range, see Figure 26 and Figure 27.
4
Sample tested during initial release to ensure compliance.
5
This device is operational with an external reference in the range of 0.1 V to V
DD
. See the Reference section for more information.
6
Measured with a midscale dc analog input.
1
2
Rev. E | Page 4 of 30
Data Sheet
TIMING SPECIFICATIONS
AD7938-6
V
DD
= V
DRIVE
= 2.7 V to 5.25 V, internal/external V
REF
= 2.5 V, unless otherwise noted; f
CLKIN
= 10MHz, f
SAMPLE
= 625 kSPS; T
A
= T
MIN
to
T
MAX
, unless otherwise noted.
Table 3.
Parameter
1
f
CLKIN 2
t
QUIET
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
10
t
11
t
12
t
13 3
t
14 4
t
15
t
16
t
17
t
18
t
19
t
20
t
21
t
22
1
Limit at T
MIN
, T
MAX
700
10
30
10
15
50
0
0
10
10
10
10
0
0
30
30
3
50
0
0
10
0
10
40
15.7
7.8
Unit
kHz min
MHz max
ns min
ns min
ns min
ns max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns min
ns max
ns min
ns min
ns min
ns min
ns min
ns max
ns min
ns min
Description
CLKIN frequency
Minimum time between end of read and start of next conversion, that is, time from when
the data bus goes into three-state until the next falling edge of CONVST.
CONVST pulse width.
CONVST falling edge to CLKIN falling edge setup time.
CLKIN falling edge to BUSY rising edge.
CS to WR setup time.
CS to WR hold time.
WR pulse width.
Data setup time before WR.
Data hold after WR.
New data valid before falling edge of BUSY.
CS to RD setup time.
CS to RD hold time.
RD pulse width.
Data access time after RD.
Bus relinquish time after RD.
Bus relinquish time after RD.
HBEN to RD setup time.
HBEN to RD hold time.
Minimum time between reads/writes.
HBEN to WR setup time.
HBEN to WR hold time.
CLKIN falling edge to BUSY falling edge.
CLKIN low pulse width.
CLKIN high pulse width.
Sample tested during initial release to ensure compliance. All input signals are specified with t
RISE
= t
FALL
= 5 ns (10% to 90% of V
DD
) and timed from a voltage level of
1.6 V. All timing specifications given above are with a 25 pF load capacitance (see Figure 36, Figure 37, Figure 38, and Figure 39).
2
Minimum CLKIN for specified performance, with slower CLKIN frequencies performance specifications apply typically.
3
The time required for the output to cross 0.4 V or 2.4 V.
4
t
14
is derived from the measured time taken by the data outputs to change 0.5 V. The measured number is then extrapolated back to remove the effects of charging or
discharging the 25 pF capacitor. This means that the time, t
14
, quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the
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