BUK9K30-80E
12 May 2018
Dual N-channel 80 V, 30 mΩ logic level MOSFET
Product data sheet
1. General description
Dual Logic level N-channel MOSFET in an LFPAK56D (Dual Power-SO8) package using
TrenchMOS technology. This product has been designed and qualified to AEC-Q101 standard for
use in high performance automotive applications.
2. Features and benefits
•
•
•
•
•
Dual MOSFET
AEC-Q101 compliant
Repetitive avalanche rated
Suitable for thermally demanding environments due to 175 °C rating
True logic level gate with V
GS(th)
rating of greater than 0.5 V at 175 °C
3. Applications
•
•
•
•
12 V, 24 V and 48 V automotive systems
Motors, lamps and solenoid control
Transmission control
Ultra high performance power switching
4. Quick reference data
Table 1. Quick reference data
Symbol
V
DS
I
D
P
tot
R
DSon
Parameter
drain-source voltage
drain current
total power dissipation
drain-source on-state
resistance
gate-drain charge
Conditions
25 °C ≤ T
j
≤ 175 °C
V
GS
= 5 V; T
mb
= 25 °C;
Fig. 2
T
mb
= 25 °C;
Fig. 1
V
GS
= 5 V; I
D
= 5 A; T
j
= 25 °C;
Fig. 11
Min
-
-
-
-
Typ
-
-
-
21
Max
80
17
53
30
Unit
V
A
W
mΩ
Limiting values FET1 and FET2
Static characteristics FET1 and FET2
Dynamic characteristics FET1 and FET2
Q
GD
I
D
= 5 A; V
DS
= 64 V; V
GS
= 5 V;
T
j
= 25 °C;
Fig. 13; Fig. 14
I
S
= 5 A; dI
S
/dt = -100 A/µs; V
GS
= 0 V;
V
DS
= 25 V; T
j
= 25 °C
-
6.2
-
nC
Source-drain diode FET1 and FET2
Q
r
recovered charge
-
30.8
-
nC
Nexperia
BUK9K30-80E
Dual N-channel 80 V, 30 mΩ logic level MOSFET
5. Pinning information
Table 2. Pinning information
Pin
1
2
3
4
5
6
7
8
Symbol Description
S1
G1
S2
G2
D2
D2
D1
D1
source1
gate1
source2
gate2
drain2
drain2
drain1
drain1
1
2
3
4
S1
G1
S2
G2
mbk725
Simplified outline
8
7
6
5
Graphic symbol
D1 D1
D2 D2
LFPAK56D (SOT1205)
6. Ordering information
Table 3. Ordering information
Type number
BUK9K30-80E
Package
Name
LFPAK56D
Description
plastic, single ended surface mounted package (LFPAK56D); 8
leads
Version
SOT1205
7. Marking
Table 4. Marking codes
Type number
BUK9K30-80E
Marking code
93080E
BUK9K30-80E
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2018. All rights reserved
Product data sheet
12 May 2018
2 / 12
Nexperia
BUK9K30-80E
Dual N-channel 80 V, 30 mΩ logic level MOSFET
8. Limiting values
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
V
DS
V
DGR
V
GS
P
tot
I
D
I
DM
T
stg
T
j
I
S
I
SM
E
DS(AL)S
Parameter
drain-source voltage
drain-gate voltage
gate-source voltage
total power dissipation
drain current
peak drain current
storage temperature
junction temperature
source current
peak source current
non-repetitive drain-
source avalanche
energy
T
mb
= 25 °C
pulsed; t
p
≤ 10 µs; T
mb
= 25 °C
I
D
= 17 A; V
sup
≤ 80 V; R
GS
= 50 Ω;
V
GS
= 5 V; T
j(init)
= 25 °C; unclamped;
Fig. 4
[3] [4]
Conditions
25 °C ≤ T
j
≤ 175 °C
R
GS
= 20 kΩ
DC; T
j
≤ 175 °C
Pulsed; T
j
≤ 175 °C
T
mb
= 25 °C;
Fig. 1
V
GS
= 5 V; T
mb
= 25 °C;
Fig. 2
V
GS
= 5 V; T
mb
= 100 °C;
Fig. 2
pulsed; t
p
≤ 10 µs; T
mb
= 25 °C;
Fig. 3
[1] [2]
Min
-
-
-10
-15
-
-
-
-
-55
-55
-
-
-
Max
80
80
10
15
53
17
12
68
175
175
17
68
72
Unit
V
V
V
V
W
A
A
A
°C
°C
A
A
mJ
Limiting values FET1 and FET2
Source-drain diode FET1 and FET2
Avalanche ruggedness FET1 and FET2
[1]
[2]
[3]
[4]
Accumulated Pulse duration up to 50 hours delivers zero defect ppm.
Significantly longer life times are achieved by lowering T
j
and or V
GS
.
Single-pulse avalanche rating limited by maximum junction temperature of 175 °C.
Refer to application note AN10273 for further information.
BUK9K30-80E
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2018. All rights reserved
Product data sheet
12 May 2018
3 / 12
Nexperia
BUK9K30-80E
Dual N-channel 80 V, 30 mΩ logic level MOSFET
120
P
der
(%)
80
03aa16
I
D
(A)
20
aaa-026806
15
10
40
5
0
0
50
100
150
T
mb
(°C)
200
0
0
25
50
75
100
125
150 175
T
mb
(°C)
200
V
GS
≥ 5 V
Fig. 2.
Fig. 1.
10
2
Limit R
DSon
= V
DS
/ I
D
t
p
= 10 µs
100 µs
Normalized total power dissipation as a
function of mounting base temperature
Continuous drain current as a function of
mounting base temperature, FET1 and FET2
aaa-026885
I
D
(A)
10
1
DC
10
-1
1 ms
10 ms
100 ms
10
-2
10
-1
1
10
10
2
V
DS
(V)
10
3
T
mb
= 25 °C; I
DM
is a single pulse
Fig. 3.
Safe operating area; continuous and peak drain currents as a function of drain-source voltage, FET1 and
FET2
BUK9K30-80E
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2018. All rights reserved
Product data sheet
12 May 2018
4 / 12
Nexperia
BUK9K30-80E
Dual N-channel 80 V, 30 mΩ logic level MOSFET
I
AL
(A)
10
2
aaa-026807
10
(1)
1
(2)
(3)
10
-1
10
-2
10
-3
10
-2
10
-1
1
t
AL
(ms)
10
(1) T
j (init)
= 25°C; (2) T
j (init)
= 150°C; (3) Repetitive Avalanche
Fig. 4.
Avalanche rating; avalanche current as a function of avalanche time, FET1 and FET2
9. Thermal characteristics
Table 6. Thermal characteristics
Symbol
R
th(j-mb)
Parameter
thermal resistance
from junction to
mounting base
thermal resistance
from junction to
ambient
10
Conditions
Fig. 5
Min
-
Typ
-
Max
2.84
Unit
K/W
R
th(j-a)
Minimum footprint; mounted on a
printed circuit board
-
95
-
K/W
003aal072
Z
th(j-mb)
(K/W)
1
δ = 0.5
0.2
0.1
10
-1
0.05
0.02
single shot
P
δ=
t
p
T
t
p
10
-2
10
-6
10
-5
10
-4
10
-3
10
-2
10
-1
t
T
t
p
(s)
1
Fig. 5.
Transient thermal impedance from junction to mounting base as a function of pulse duration, FET1 and
FET2
BUK9K30-80E
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2018. All rights reserved
Product data sheet
12 May 2018
5 / 12
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