SI5342H-D-GM datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > The embedded processor and controller> Microcontrollers and processors> SI5342H-D-GM

SI5342H-D-GM: DescriptionProcessor Specific Clock Generator, 2750MHz, CMOS, QFN-44; CategoryThe embedded processor and controller Microcontrollers and processors; File Size1MB，56 Pages; ManufacturerSilicon Laboratories Inc; Environmental Compliance

Download Datasheet Parametric Compare View All

SI5342H-D-GM Online Shopping

Suppliers	Part Number	Price	MOQ	In stock
	SI5342H-D-GM	-	-	View	Buy Now

SI5342H-D-GM Overview

Processor Specific Clock Generator, 2750MHz, CMOS, QFN-44

SI5342H-D-GM Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Objectid	8207139856
package instruction	QFN-44
Reach Compliance Code	compliant
ECCN code	EAR99
Samacsys Manufacturer	Silicon Labs
Samacsys Modified On	2021-05-20 12:59:41
Other features	ALSO REQUIRES 3.3V SUPPLY
JESD-30 code	S-XQCC-N44
length	7 mm
Number of terminals	44
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Maximum output clock frequency	2750 MHz
Package body material	UNSPECIFIED
encapsulated code	HVQCCN
Package shape	SQUARE
Package form	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Master clock/crystal nominal frequency	54 MHz
Maximum seat height	0.9 mm
Maximum supply voltage	1.89 V
Minimum supply voltage	1.71 V
Nominal supply voltage	1.8 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	NO LEAD
Terminal pitch	0.5 mm
Terminal location	QUAD
width	7 mm
uPs/uCs/peripheral integrated circuit type	CLOCK GENERATOR, PROCESSOR SPECIFIC

Preview

Download Datasheet

View All

Si5344H/42H Rev D

I G H

-F

R E Q U E N C Y

, U

LTRA

-L

O W

I T T E R

T T E N U A T O R

L O C K

W I T H

IG ITA LLY

- C

O N T R O L L E D

S C I L L A T O R

Features



High-speed outputs generate an



ultra-low jitter output up to 2.75 GHz

Up to four Multi-Synth outputs



generate any frequency up to

717.5 MHz



Input frequency range:



8 kHz to 750 MHz



Maximum Output frequency:





High-Frequency Mode: 2.75 GHz





MultiSynth Mode: 717.5 MHz

Jitter performance:

High Frequency Mode:

<50 fs typ (1 MHz–40 MHz)



MultiSynth Mode:

<150 fs typ (12 kHz–20 MHz)



Programmable jitter attenuation



bandwidth: 10 Hz to 4 kHz

Highly configurable outputs



compatible with LVDS, LVPECL,

LVCMOS, CML, and HCSL with

programmable voltage swing and



common mode





LVPECL-only in High Frequency



Mode



Status monitoring (LOS, OOF, LOL)

Hitless input clock switching:

automatic or manual

Automatic free-run and holdover

modes

Glitchless on the fly output

frequency changes

Locks to gapped clock inputs

DCO mode: as low as 0.001 ppb

steps.

Core voltage



: 1.8 V ±5%



DDA

3.3 V ±5%

Independent output supply pins:

3.3 V, 2.5 V, or 1.8 V

Serial interface: I

C or SPI

In-circuit programmable with

non-volatile OTP memory

ClockBuilder Pro

software

simplifies device configuration

Si5342H: 2 input, 2 output, QFN44

Si5344H, 2 input, 4 output, QFN44

Temperature range: –40 to +85 °C

Pb-free, RoHS-6 compliant

Ordering Information:

See Section 7.

Pin Assignments

Si5342H 44QFN

Top View

I2C_SEL

RSVD_GND

VDDS

VDD

IN0

VDD

IN1

IN_SEL0

VDDA

INTR

VDD

LOS1

LOS0

VDDS

LOS_XAXB

LOL

VDDS

OUT1

VDDO1

Applications



GND

Pad

100G/200G/400G Optical

Transceivers



Wireless base-stations

VDDA

OUT0

VDD

SDA/SDIO

A1/SDO

A0/CS

RST

SDA/SDIO

A1/SDO

A0/CS

Rev. 1.0 9/16

VDDO0

OUT0

SCLK

OUT0

VDD

RST

This specialized jitter attenuating clock multiplier combines fourth-generation

DSPLL with ultra-low phase jitter and MultiSynth™ technologies to enable high

data rate coherent optical transceiver design. Up to four outputs can be assigned

to High Frequency Mode capable of up to 2.75 GHz at 50 fs-rms typical phase

jitter (1 MHz-40 MHz). Each output may also be configured as MultiSynth Mode

any-frequency outputs when added frequency flexibility is required, such as

clocking Forward Error Correction (FEC) while still delivering <150 fs-rms typical

phase jitter (12 kHz-20 MHz). The Si5344H and Si5342H also feature DCO-

control with as low as 0.001 ppb step control and locks to gapped clock inputs.

These devices are programmable via a serial interface with in-circuit

programmable non-volatile memory (NVM) so that they always power up with a

known frequency configuration. The loop filter is fully integrated on-chip

eliminating the risk of potential noise coupling associated with discrete solutions.

Programming the Si5342H/44H is made easy with Silicon Labs’

ClockBuilderPro

software. Factory preprogrammed devices are also available.

Si5344H 44QFN

Top View

I2C_SEL

IN_SEL1

VDDO3

VDDO0

OUT0

SCLK

Description

OUT3

IN1

IN_SEL0

XGND

VDDA

OUT3

VDD

IN0

VDD

INTR

VDD

OUT2

VDDO2

LOS_XAXB

LOL

VDDS

OUT1

VDDO1

GND

Pad

Si5344H/42H

Si5344H/42H

ABLE

ON TENTS

1. Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

2. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

3. Typical Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.1. Frequency Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.2. DSPLL Loop Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.3. Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.4. External Reference (XA/XB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4.5. Digitally Controlled Oscillator (DCO) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4.6. Inputs (IN0, IN1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

4.7. Fault Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

4.8. Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

4.9. Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

4.10. In-Circuit Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

4.11. Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

4.12. Custom Factory Preprogrammed Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

4.13. Enabling Features and/or Configuration Settings Unavailable in ClockBuilder Pro for

Factory Preprogrammed Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

5. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

5.1. Addressing Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

5.2. High-Level Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

6. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

7. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

7.1. Ordering Part Number Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

8. Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

8.1. 7x7 mm 44-QFN Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

9. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

10. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

11. Device Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

Rev. 1.0

SI5342H-D-GM Related Products

	SI5342H-D-GM	SI5342H-D04990-GM	SI5344H-D-GM	SI5344H-D05851-GM	SI5344H-EVB	SI5344H-D-GMR	SI5344H-D05851-GMR	SI5342H-D-GMR	SI5342H-D04990-GMR
Description	Processor Specific Clock Generator, 2750MHz, CMOS, QFN-44	100G/400G COHERENT OPTICS CLOCK,	HI FREQ LO JITR ATTEN CLK W OSC	100G/400G COHERENT OPTICS CLOCK,	EVAL BOARD SI5344H/SI5342H	IC BASE/BLANK PROTOTYPE 44QFN	100G/400G COHERENT OPTICS CLOCK,	IC BASE/BLANK PROTOTYPE 44QFN	100G/400G COHERENT OPTICS CLOCK,

Recommended Resources

Leyin brand HA-01A hearing aid circuit

Optical signal receiving circuit

Intelligent pressure measurement circuit

24V regulated power supply circuit with current compensation

SB-50ALTX receiver

Computer motherboard circuit diagram 810 3_08

Makefile Kconfig association: Simple HelloWord.c program #config config HELLOWORD bool "helloword" depends on HelloWord.c help ......... #Makefile obj-$(CONFIG_HELLOWORD)+=HelloWord.c Do I need to write gcc HelloWord.c command in ...; shinecl Embedded System

A novice's talk on analog integrated circuit design: [i=s]This post was last edited by tee是裤 on 2014-9-17 17:31[/i] [align=left][color=#222222][size=14px]Reposted from ADI Chinese Technical Support Community:[/size][/color][color=#222222]https:[/color][...; tee是裤子 Talking about work

Where can I download the PPC2002 Chinese simulator?: I have been looking for it for a long time but can't find it. Does anyone know where to find the link?...; axiaoyeah Embedded System

What do you most want to do after the epidemic is over?: Netizens said they missed the fresh air outside, and missed the hot pot, pizza, hamburgers, French fries, spicy hot pot, grilled cold noodles, boiled fish, pickled fish, grilled fish, lamb skewers, ba...; led2015 Talking

Memory Technology Suzhou R&D Center Latest Recruitment 20180913: Memory Technology Suzhou Company/Beijing Requirements: 1. PDT Manager (Senior Product Manager) 2. Verification Manager (SOC verification is preferred) 3. Verification Engineer (both system and module ...; maggiemamaqiao1 Recruitment

KEIL debugging initialization problem: Single step debugging Vectors LDR PC, Reset_Addr LDR PC, Undef_Addr LDR PC, SWI_Addr LDR PC, PAbt_Addr LDR PC, DAbt_Addr NOP ; Reserved Vector LDR PC, IRQ_Addr LDR PC, FIQ_Addr During execution, Vecto...; fancunyuan Embedded System

Shortcut: E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF EG EH EI EJ EK EL EM EN EO EP EQ ER ES ET EU EV EW EX EY EZ F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF FG FH FI FJ FK FL FM FN FO FP FQ FR FS FT FU FV FW FX FY FZ G0 G1 G2 G3 G4 G5 G6 G7 G8 G9 GA GB GC GD GE GF GG GH GI GJ GK GL GM GN GO GP GQ GR GS GT GU GV GW GX GZ H0 H1 H2 H3 H4 H5 H6 H7 H8 HA HB HC HD HE HF HG HH HI HJ HK HL HM HN HO HP HQ HR HS HT HU HV HW HX HY HZ I1 I2 I3 I4 I5 I6 I7 IA IB IC ID IE IF IG IH II IK IL IM IN IO IP IQ IR IS IT IU IV IW IX J0 J1 J2 J6 J7 JA JB JC JD JE JF JG JH JJ JK JL JM JN JP JQ JR JS JT JV JW JX JZ K0 K1 K2 K3 K4 K5 K6 K7 K8 K9 KA KB KC KD KE KF KG KH KI KJ KK KL KM KN KO KP KQ KR KS KT KU KV KW KX KY KZ

Popular Components