2.5V and 3.3V CMOS PLL
Clock Generator and Driver
MPC9315
OBSOLETE
The MPC9315 is a 2.5 V and 3.3 V compatible, PLL based clock generator
designed for low-skew clock distribution in low-voltage mid-range to
high-performance telecom, networking and computing applications. The
MPC9315 offers 8 low-skew outputs and 2 selectable inputs for clock
redundancy. The outputs are configurable and support 1:1, 2:1, 4:1, 1:2 and 1:4
output to input frequency ratios. In addition, a selectable output 180 phase
control supports advanced clocking schemes with inverted clock signals. The
MPC9315 is specified for the extended temperature range of –40 to +85C.
Features
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Configurable 8 Outputs LVCMOS PLL Clock Generator
Compatible to Various Microprocessors Such As PowerQUICC I and II
Wide Range Output Clock Frequency of 18.75 to 160 MHz
2.5 V and 3.3 V CMOS Compatible
Designed for Mid-Range to High-Performance Telecom, Networking and
Computer Applications
Fully Integrated PLL Supports Spread Spectrum Clocking
Supports Applications Requiring Clock Redundancy
Max. Output Skew of 120 ps (80 ps Within One Bank)
Selectable Output Configurations (1:1, 2:1, 4:1, 1:2, 1:4 Frequency Ratios)
Two Selectable LVCMOS Clock Inputs
External PLL Feedback Path and Selectable Feedback Configuration
Tristable Outputs
32-Lead LQFP Package
Ambient Operating Temperature Range of -40 to +85C
32-Lead Pb-Free Package
MPC9315
LOW VOLTAGE
2.5 V AND 3.3 V PLL
CLOCK GENERATOR
AC SUFFIX
32-LEAD LQFP PACKAGE
Pb-FREE PACKAGE
CASE 873A-04
Functional Description
The MPC9315 utilizes PLL technology to frequency and phase lock its outputs onto an input reference clock. Normal operation
requires a connection of one of the device outputs to the selected feedback (FB0 or FB1) input to close the PLL feedback path.
The reference clock frequency and the output divider for the feedback path determine the VCO frequency. Both must be selected
to match the VCO frequency range. With available output dividers of divide-by-1, divide-by-2 and divide-by-4, the internal VCO
of the MPC9315 is running at either 1x, 2x or 4x of the reference clock frequency. The frequency of the QA, QB, QC output groups
is either the equal, one half or one fourth of the selected VCO frequency and can be configured for each output bank using the
FSELA, FSELB and FSELC pins, respectively. The available output to input frequency ratios are 4:1, 2:1, 1:1, 1:2 and 1:4. The
REF_SEL pin selects one of the two available LVCMOS compatible reference input (CLK0 and CLK1) supporting clock redundant
applications. The selectable feedback input pin allows the user to select different feedback configurations and input to output
frequency ratios. The MPC9315 also provides a static test mode when the PLL supply pin (V
CCA
) is pulled to logic low state
(GND). In test mode, the selected input reference clock is routed directly to the output dividers bypassing the PLL. The test mode
is intended for system diagnostics, test and debug purposes. This test mode is fully static and the minimum clock frequency spec-
ification does not apply. The outputs can be disabled by deasserting the OE pin (logic high state). In PLL mode, deasserting OE
causes the PLL to lose lock due to no feedback signal presence at FB0 or FB1. Asserting OE will enable the outputs and close
the phase locked loop, also enabling the PLL to recover to normal operation. The MPC9315 is fully 2.5 V and 3.3 V compatible
and requires no external loop filter components. All inputs accept LVCMOS signals while the outputs provide LVCMOS compat-
ible levels with the capability to drive terminated 50
transmission lines. For series terminated transmission lines, each of the
MPC9315 outputs can drive one or two traces giving the devices an effective fanout of 1:18. The device is packaged in a 7x7 mm
2
32-lead LQFP package.
The fully integrated PLL of the MPC9315 allows the low skew outputs to lock onto a clock input and distribute it with essentially
zero propagation delay to multiple components on the board. In zero-delay buffer mode, the PLL minimizes phase offset between
the outputs and the reference signal.
©2016 Integrated Device Technology, Inc.
1
Revision 6, October 4, 2016
OBSOLETE
MPC9315 Datasheet
V
CCA
V
CC
6
CLK0
CLK1
(Pulldown)
(Pulldown)
Bank A
0
Ref
1
FB
CLK2
75 – 160 MHz
CLK4
1
1
Bank B
QB0
QA1
PLL
CLK
0
0
QA0
REF_SEL
(Pulldown)
FB0
FB1
FB_SEL
FSELA
PSELA
FSELB
(Pulldown)
(Pulldown)
(Pulldown)
0
1
0
1
QB1
QB2
QB3
(Pulldown)
(Pulldown)
(Pullup)
0
1
Bank C
QC0
QC1
FSELC
OE
(Pullup)
(Pulldown)
GND
6
Figure 1. MPC9315 Logic Diagram
GND
GND
18
QB0
QB1
QB2
24
GND
QA1
QA0
V
CC
FSELC
FSELB
FSELA
GND
25
26
27
28
23
22
21
20
19
QB3
17
16
15
14
13
V
CC
QC0
QC1
GND
OE
PSELA
FBSEL
V
CC
12
11
10
9
8
GND
V
CC
MPC9315
29
30
31
32
1
2
3
4
5
6
7
CLK0
REF_SEL
CLK1
V
CCA
V
CC
V
CC
FB0
Figure 2. Pinout: 32-Lead Package Pinout
(Top View)
© Integrated Device Technology, Inc.
2
FB1
Revision 6, October 4, 2016
OBSOLETE
MPC9315 Datasheet
Table 1. Pin Configuration
Pin
CLK0
CLK1
FB0
FB1
REF_SEL
FB_SEL
FSELA
FSELB
FSELC
PSELA
QA0, QA1
QB0 to QB3
QC0, QC1
OE
V
CCA
V
CC
GND
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Output
Output
Input
I/O
Type
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Supply
Supply
Ground
Reference clock input
Alternative clock input
PLL feedback input
Alternative feedback input
Selects clock input reference clock input, default low (pull-down)
Selects PLL feedback clock input, default low (pull-down)
Selects divider ratio of bank A outputs, default low (pull-down)
Selects divider ratio of bank B outputs, default low (pull-up)
Selects divider ratio of bank C outputs, default low (pull-up)
Selects phase of bank A outputs
Bank A outputs
Bank B outputs
Bank C outputs
Output tristate
Analog (PLL) positive supply voltage. Requires external RC filter
Digital positive supply voltage
Digital negative supply voltage (ground)
Function
Table 2. Function Table
Control
REF_SEL
FB_SEL
FSELA
FSELB
FSELC
PSELA
V
CCA
MR
OE
Default
0
0
0
1
1
0
none
0
0
CLK0
FB0
QAx = VCO clock frequency
QBx = VCO clock frequency
QCx = VCO clock frequency
2
0° (QA0, QA1 non-inverted)
V
CCA
= GND, PLL off and bypassed for static test and diagnosis
Normal operation
Outputs enabled
0
CLK1
FB1
QA0, QA1 = VCO clock frequency
2
QB0 - QB3 = VCO clock frequency
2
QC0, QC1 = VCO clock frequency
4
180 (QA0, QA1 inverted)
V
CCA
= 3.3 or 2.5 V, PLL enabled
Reset (VCO clamped to min. range)
Outputs disabled (tristate), open PLL loop
1
Table 3. Absolute Maximum Ratings
(1)
Symbol
V
CC
V
IN
V
OUT
I
IN
I
OUT
T
S
Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Current
DC Output Current
Storage temperature
-55
Characteristics
Min
-0.3
-0.3
-0.3
Max
4.6
V
CC
+0.3
V
CC
+0.3
20
50
125
Unit
V
V
V
mA
mA
C
1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these
conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under
absolute-maximum-rated conditions is not implied.
© Integrated Device Technology, Inc.
3
Revision 6, October 4, 2016
OBSOLETE
MPC9315 Datasheet
Table 4. General Specifications
Symbol
V
TT
MM
HBM
LU
C
PD
C
IN
Characteristics
Output Termination Voltage
ESD (Machine Model)
ESD (Human Body Model)
Latch-Up
Power Dissipation Capacitance
Input Capacitance
200
2000
200
10
4.0
Min
Typ
V
CC
2
Max
Unit
V
V
V
mA
pF
pF
Per output
Inputs
Condition
Table 5. DC Characteristics
(V
CC
= 3.3 V ± 5%, T
A
= -40° to 85°C)
Symbol
V
IH
V
IL
V
OH
V
OL
Z
OUT
I
IN
I
CCA
I
CCQ
Characteristics
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Output Impedance
Input Current
(2)
Maximum PLL Supply Current
Maximum Quiescent Supply Current
3.5
14 - 17
200
7.0
1.0
2.4
0.55
0.30
Min
2.0
Typ
Max
V
CC
+ 0.3
0.8
Unit
V
V
V
V
V
A
mA
mA
V
IN
= V
CC
or
GND
V
CCA
Pin
All V
CC
Pins
Condition
LVCMOS
LVCMOS
I
OH
= –24
mA
(1)
I
OL
= 24 mA
(1)
I
OL
= 12 mA
1. The MPC9315 is capable of driving 50
transmission lines on the incident edge. Each output drives one 50
parallel terminated
transmission line to a termination voltage of V
TT
. Alternatively, the device drives up to two 50
series terminated transmission lines.
2. Inputs have pull-up or pull-down resistors affecting the input current.
© Integrated Device Technology, Inc.
4
Revision 6, October 4, 2016
OBSOLETE
MPC9315 Datasheet
Table 6. AC Characteristics
(V
CC
= 3.3 V ± 5%, T
A
= -40° to 85°C)
(1)
Symbol
f
ref
Characteristics
Input Frequency
1
feedback
2
feedback
4
feedback
PLL bypass mode
f
VCO
f
MAX
VCO Lock Range
Maximum Output Frequency
1
output
2
output
4
output
Min
100
(2)
37.50
18.75
0
75
(2)
75
37.50
18.75
25
Typ
Max
160
80
40
TBD
160
160
80
40
75
1.0
-150
+150
80
120
45
0.1
50
55
1.0
10
10
1
feedback
2
feedback
4
feedback
(1)
(1)
(1)
TBD
2.0 - 20
0.6 - 6.0
10
8.0
8.0 - 25
(3)
22
15
TBD
1.0
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
%
ns
ps
ps
ps
%
ns
ns
ns
MHz
MHz
MHz
ps
ps
ps
ms
RMS value
RMS value
RMS value
0.55 to 2.4 V
0.8 to 2.0 V
PLL locked
Condition
PLL locked
PLL locked
PLL locked
V
CCA
= GND
f
refDC
t
r
, t
f
t
()
t
SK()
DC
t
r
, t
f
t
PLZ, HZ
t
PZL, LZ
BW
Reference Input Duty Cycle
CLK0, CLK1 Input Rise/Fall Time
Propagation Delay
(Static Phase Offset)
Output-to-Output Skew
Output Duty Cycle
Output Rise/Fall Time
Output Disable Time
Output Enable Time
PLL closed loop bandwidth
CLK0 or CLK1 to FB
Within one bank
Any output
t
JIT(CC)
t
JIT(PER)
t
JIT()
t
LOCK
Cycle-to-Cycle Jitter
Period Jitter
I/O Phase Jitter
Maximum PLL Lock Time
1. AC characteristics apply for parallel output termination of 50
to V
TT
.
2. The VCO range in
1
feedback configuration (e.g. QAx connected to FBx and FSELA = 0) is limited to 100
f
VCO
160 MHz. Please see
next revision of the MPC9315 for improved VCO frequency range.
3. I/O jitter depends on VCO frequency. Please see
Applications Information
section for I/O jitter versus VCO frequency characteristics.
Table 7. DC Characteristics
(V
CC
= 2.5 V ± 5%, T
A
= -40° to 85°C)
Symbol
V
IH
V
IL
V
OH
V
OL
Z
OUT
I
IN
I
CCA
I
CCQ
Characteristics
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Output Impedance
Input Current
(2)
Maximum PLL Supply Current
Maximum Quiescent Supply Current
2.0
17 - 20
200
5.0
1.0
1.8
0.6
Min
1.7
Typ
Max
V
CC
+ 0.3
0.7
Unit
V
V
V
V
A
mA
mA
V
IN
= V
CC
or
GND
V
CCA
Pin
All V
CC
Pins
Condition
LVCMOS
LVCMOS
I
OH
= –15
mA
(1)
I
OL
= 15 mA
1. The MPC9315 is capable of driving 50
transmission lines on the incident edge. Each output drives one 50
parallel terminated
transmission line to a termination voltage of V
TT
. Alternatively, the device drives up to two 50
series terminated transmission lines.
2. Inputs have pull-up or pull-down resistors affecting the input current.
© Integrated Device Technology, Inc.
5
Revision 6, October 4, 2016
OBSOLETE
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