A25L40P Series
4 Mbit, Low Voltage, Serial Flash Memory
Preliminary
Document Title
4 Mbit, Low Voltage, Serial Flash Memory With 85MHz SPI Bus Interface
Revision History
Rev. No.
0.0
0.1
0.2
0.3
With 85MHz SPI Bus Interface
History
Initial issue
Add the Fast Read Dual Operation Instruction
Add QFN 8L (5 x 6mm) package type
Add QFN 8L (5 x 6mm) package outline dimensions
Modify the Part No. for Top/Bottom boot sector type
Add DIP 8(300mil) package type
Modify the maximum clock rate to 75MHz
Issue Date
August 29, 2006
April 4, 2006
April 20, 2006
September 5, 2006
Remark
Preliminary
0.4
Add transient voltage (<20ns) on any pin to ground potential spec.
Add the maximum clock rate of 3.0V~3.6V : 85MHz
May 25, 2007
PRELIMINARY
(May, 2007, Version 0.4)
AMIC Technology Corp.
A25L40P Series
4 Mbit, Low Voltage, Serial Flash Memory
Preliminary
FEATURES
4 Mbit of Flash Memory
Flexible Sector Architecture (4/4/8/16/32)KB/64x7 KB
Bulk Erase (4 Mbit) in 6s (typical)
Sector Erase (512 Kbit) in 1s (typical)
Page Program (up to 256 Bytes) in 3ms (typical)
2.7 to 3.6V Single Supply Voltage
SPI Bus Compatible Serial Interface
85MHz Clock Rate (maximum)
Deep Power-down Mode 1µA (typical)
Top or Bottom boot block configuration available
Electronic Signatures
-
JEDEC Standard two-Byte Signature (2013h)
-
RES Instruction, One-Byte, Signature (12h), for backward
compatibility
Package options
-
8-pin SOP (150mil or 209mil), 16-pin SOP, 8-pin DIP
(300mil) or 8-pin QFN
- All Pb-free (Lead-free) products are RoHS compliant
With 85MHz SPI Bus Interface
GENERAL DESCRIPTION
The A25L40P is a 4 Mbit (512K x 8) Serial Flash Memory, with
advanced write protection mechanisms, accessed by a high
speed SPI-compatible bus.
The memory can be programmed 1 to 256 bytes at a time, using
the Page Program instruction.
The memory is organized as 8 sectors, each containing 256
pages. Each page is 256 bytes wide. Thus, the whole memory
can be viewed as consisting of 2048 pages, or 524,288 bytes.
The whole memory can be erased using the Bulk Erase
instruction, or a sector at a time, using the Sector Erase
instruction.
Pin Configurations
SO8 Connections
SO16 Connections
A25L40P
A25L40P
S
Q
W
V
SS
1
2
3
4
8 V
CC
7 HOLD
6 C
5 D
HOLD
V
CC
DU
DU
DU
DU
S
Q
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
C
D
DU
DU
DU
DU
V
SS
W
Note:
DU = Do not Use
DIP8 Connections
QFN8 Connections
A25L40P
S
Q
W
V
SS
1
2
3
4
8 V
CC
7 HOLD
6 C
5 D
S
Q
W
V
SS
A25L40P
1
2
3
4
8
7
6
5
V
CC
HOLD
C
D
PRELIMINARY
(May, 2007, Version 0.4)
1
AMIC Technology Corp.
A25L40P Series
SIGNAL DESCRIPTION
Serial Data Output (Q).
This output signal is used to transfer
data serially out of the device. Data is shifted out on the
falling edge of Serial Clock (C).
Serial Data Input (D).
This input signal is used to transfer
data serially into the device. It receives instructions,
addresses, and the data to be programmed. Values are
latched on the rising edge of Serial Clock (C).
Serial Clock (C).
This input signal provides the timing of the
serial interface. Instructions, addresses, or data present at
Serial Data Input (D) are latched on the rising edge of Serial
Clock (C). Data on Serial Data Output (Q) changes after the
falling edge of Serial Clock (C).
Chip Select (
S
).
When this input signal is High, the device is
deselected and Serial Data Output (Q) is at high impedance.
Unless an internal Program, Erase or Write Status Register
cycle is in progress, the device will be in the Standby mode
(this is not the Deep Power-down mode). Driving Chip Select
(
S
) Low enables the device, placing it in the active power
mode.
After Power-up, a falling edge on Chip Select (
S
) is required
prior to the start of any instruction.
Hold (
HOLD
).
The Hold (
HOLD
) signal is used to pause
any serial communications with the device without
deselecting the device.
During the Hold condition, the Serial Data Output (Q) is high
impedance, and Serial Data Input (D) and Serial Clock (C)
are Don’t Care. To start the Hold condition, the device must
be selected, with Chip Select (
S
) driven Low.
Write Protect (
W
).
The main purpose of this input signal is
to freeze the size of the area of memory that is protected
against program or erase instructions (as specified by the
values in the BP2, BP1 and BP0 bits of the Status Register).
SPI MODES
These devices can be driven by a microcontroller with its SPI
peripheral running in either of the two following modes:
– CPOL=0, CPHA=0
– CPOL=1, CPHA=1
For these two modes, input data is latched in on the rising
edge of Serial Clock (C), and output data is available from the
falling edge of Serial Clock (C).
The difference between the two modes, as shown in Figure 2,
is the clock polarity when the bus master is in Stand-by mode
and not transferring data:
– C remains at 0 for (CPOL=0, CPHA=0)
– C remains at 1 for (CPOL=1, CPHA=1)
PRELIMINARY
(May, 2007, Version 0.4)
3
AMIC Technology Corp.
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