A25L16P Series
16 Mbit, Low Voltage, Serial Flash Memory
Preliminary
Document Title
16 Mbit, Low Voltage, Serial Flash Memory With 85MHz SPI Bus Interface
Revision History
Rev. No.
0.0
0.1
0.2
0.3
0.4
0.5
With 85MHz SPI Bus Interface
History
Initial issue
Change part no. from A25L160P to A25L16P
Change the frequency to 70 MHz
Add the Fast Read Dual Input-Output Mode
Add QFN 8L (5 x 6mm) package type
Top or bottom boot block configuration available
Change the frequency to 85 MHz
Remove the REMS mode
Correct the A25LPT memory organization of Table 2-1
Reduce the options of protected area size to all sectors
protected and all sectors unprotected
Modify the I
CC1
and I
CC3
of Table 10
Modify the t
W
and t
BE
of Table 11
Issue Date
March 10, 2006
March 23, 2006
March 27, 2006
April 20, 2006
December 5, 2006
February 6, 2007
Remark
Preliminary
0.6
Add transient voltage (<20ns) on any pin to ground potential spec.
April 24, 2007
PRELIMINARY
(April, 2007, Version 0.6)
AMIC Technology Corp.
A25L16P Series
16 Mbit, Low Voltage, Serial Flash Memory
Preliminary
FEATURES
16 Mbit of Flash Memory
Flexible Sector Architecture (4/4/8/16/32)KB/64x31 KB
Bulk Erase (16 Mbit) in 20s (typical)
Sector Erase (512 Kbit) in 1s (typical)
Page Program (up to 256 Bytes) in 1.5ms (typical)
2.7 to 3.6V Single Supply Voltage
SPI Bus Compatible Serial Interface
85MHz Clock Rate (maximum)
Fast Read Dual Operation Instruction (3Bh/BBh)
Deep Power-down Mode 1µA (typical)
Top or Bottom Boot Block Configuration Available
Electronic Signature
-
JEDEC Standard Two-Byte Signature (2015h, Bottom;
or 2025, Top)
-
RES Instruction, One-Byte, Signature (14h)
Package Options
- 8-pin SOP (209mil), 16-pin SOP, or 8-pin QFN
- All Pb-free (Lead-free) products are ROHS complaint
With 85MHz SPI Bus Interface
GENERAL DESCRIPTION
The A25L16P is a 16 Mbit (2M x 8) Serial Flash Memory,
with advanced write protection mechanisms, accessed by a
high speed SPI-compatible bus.
The memory can be programmed 1 to 256 bytes at a time,
using the Page Program instruction.
The memory is organized as 32 sectors, each containing 256
pages. Each page is 256 bytes wide. Thus, the whole
memory can be viewed as consisting of 8192 pages, or
2,097,152 bytes.
The whole memory can be erased using the Bulk Erase
instruction, or a sector at a time, using the Sector Erase
instruction.
Pin Configurations
SO8 Connections
SO16 Connections
QFN8 Connections
A25L16P
A25L16P
S
DO
W
V
SS
1
2
3
4
8
7 HOLD
6 C
5 DIO
V
CC
HOLD
V
CC
DU
DU
DU
DU
S
DO
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
C
DIO
DU
DU
DU
DU
V
SS
W
A25L16P
S
DIO
W
V
SS
1
2
3
4
8
7
6
5
V
CC
HOLD
C
DO
Note:
DU = Do not Use
PRELIMINARY
(April, 2007, Version 0.6)
1
AMIC Technology Corp.
A25L16P Series
Block Diagram
HOLD
W
S
C
DIO
DO
I/O Shift Register
Control Logic
High Voltage
Generator
Address register
and Counter
256 Byte
Data Buffer
Status
Register
1FFFFFh
Y Decoder
Size of the
read-only
memory area
000FFh
00000h
256 Byte (Page Size)
X Decoder
Pin Descriptions
Pin No.
C
DIO
DO
Serial Clock
Serial Data Input
1
Serial Data Output
2
Chip Select
Write Protect
Hold
Supply Voltage
Ground
Description
Logic Symbol
V
CC
DIO
C
S
W
HOLD
A25L16P
DO
S
W
HOLD
V
CC
V
SS
V
SS
Notes:
1. The DIO is also used as an output pin when the Fast
Read Dual Output instruction and the Fast Read Dual
Input-Output instruction are executed.
2. The DO is also used as an input pin when the Fast Read
Dual Input-Output instruction is executed.
PRELIMINARY
(April, 2007, Version 0.6)
2
AMIC Technology Corp.
A25L16P Series
SIGNAL DESCRIPTION
Serial Data Output (DO).
This output signal is used to
transfer data serially out of the device. Data is shifted out on
the falling edge of Serial Clock (C).
The DO pin is also used as an input pin when the Fast Read
Dual Input-Output Function is executed.
Serial Data Input / Output (DIO).
This input signal is used to
transfer data serially into the device. It receives instructions,
addresses, and the data to be programmed. Values are
latched on the rising edge of Serial Clock (C).
The DIO pin is also used as an output pin when the Fast
Read Dual Output function and Fast Read Dual Input-Output
function are executed.
Serial Clock (C).
This input signal provides the timing of the
serial interface. Instructions, addresses, or data present at
Serial Data Input (DIO) are latched on the rising edge of
Serial Clock (C). Data on Serial Data Output (DO) changes
after the falling edge of Serial Clock (C).
Chip Select (
S
).
When this input signal is High, the device
is deselected and Serial Data Output (DO) is at high
impedance. Unless an internal Program, Erase or Write
Status Register cycle is in progress, the device will be in the
Standby mode (this is not the Deep Power-down mode).
Driving Chip Select (
S
) Low enables the device, placing it in
the active power mode.
After Power-up, a falling edge on Chip Select (
S
) is required
prior to the start of any instruction.
Hold (
HOLD
).
The Hold (
HOLD
) signal is used to pause
any serial communications with the device without
deselecting the device.
During the Hold condition, the Serial Data Output (DO) is
high impedance, and Serial Data Input (DIO) and Serial
Clock (C) are Don’t Care. To start the Hold condition, the
device must be selected, with Chip Select (
S
) driven Low.
Write Protect (
W
).
The main purpose of this input signal is
to freeze the size of the area of memory that is protected
against program or erase instructions (as specified by the
values in the BP2, BP1 and BP0 bits of the Status Register).
SPI MODES
These devices can be driven by a microcontroller with its SPI
peripheral running in either of the two following modes:
– CPOL=0, CPHA=0
– CPOL=1, CPHA=1
For these two modes, input data is latched in on the rising
edge of Serial Clock (C), and output data is available from
the falling edge of Serial Clock (C).
The difference between the two modes, as shown in Figure 2,
is the clock polarity when the bus master is in Stand-by mode
and not transferring data:
– C remains at 0 for (CPOL=0, CPHA=0)
– C remains at 1 for (CPOL=1, CPHA=1)
PRELIMINARY
(April, 2007, Version 0.6)
3
AMIC Technology Corp.
A25L16P Series
Figure 1. Bus Master and Memory Devices on the SPI Bus
SPI Interface with
(CPOL, CPHA)
= (0, 0) or (1, 1)
Bus Master
(ST6, ST7, ST9,
ST10, Other)
SDO
SDI
SCK
C Q D
C Q D
C Q D
SPI Memory
Device
CS3
CS2
CS1
S
W HOLD
SPI Memory
Device
SPI Memory
Device
S
W HOLD
S
W HOLD
Note: The Write Protect (
W
) and Hold (
HOLD
) signals should be driven, High or Low as appropriate.
Figure 2. SPI Modes Supported
CPOL
0
1
CPHA
0
1
C
C
DIO
DO
MSB
MSB
PRELIMINARY
(April, 2007, Version 0.6)
4
AMIC Technology Corp.
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