8P79818NLGI8 datasheet, PDF - EEWORLD Datasheet

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8P79818NLGI8: DescriptionIC CLOCK BUFFER 32VFQFPN; Categorysemiconductor Analog mixed-signal IC; File Size867KB，34 Pages; ManufacturerIDT (Integrated Device Technology, Inc.); Websitehttp://www.idt.com/; Environmental Compliance

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8P79818NLGI8 Overview

IC CLOCK BUFFER 32VFQFPN

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Programmable Low Additive Jitter 2:8

Buffer with Dividers and Universal Outputs

8P79818

Datasheet

Description

The device is intended to take 1 or 2 reference clocks, select

between them, using a pin or register selection and generate up to 8

outputs that may be the same as the reference frequency or

integer-divider versions of it.

The 8P79818 supports two output banks, each with its own divider

and power supply. All outputs in one bank would generate the same

output frequency, but each output can be individually controlled for

output type, output enable or even powered-off.

The device supports a serial port for configuration of the parameters

while in operation. The serial port can be selected to use the I

C or

SPI protocol. After power-up, all outputs will come up in LVDS mode

and may be programmed to other configurations over the serial port.

Outputs may be enabled or disabled under control of the OE input

pin.

The device can operate over the -40°C to +85°C temperature range.

Features

▪

Two differential inputs support LVPECL, LVDS, HCSL or LVCMOS

reference clocks

— Accepts input frequencies ranging from 1PPS (1Hz) to

700MHz

▪

Select which of the two input clocks is to be used as the reference

clock for which divider via pin or register selection

— Switchover will not generate any runt clock pulses on the

output

▪

Generates eight differential outputs

or eight LVCMOS outputs, Bank A only

— Differential outputs selectable as LVPECL, LVDS, CML or

HCSL

— Differential outputs support frequencies from 1PPS to 700MHz

— LVCMOS outputs support frequencies from 1PPS to 200MHz

— LVCMOS outputs in the same pair may be inverted or in-phase

relative to one another

▪

Outputs arranged in 2 banks of 4 outputs each

— Each bank supports a separate power supply of 3.3V, 2.5V or

1.8V

— 1.5V output voltage is also supported for LVCMOS, Bank A

only

— One divider per output bank, supporting divide ratios of 2...511

or divider bypass

▪

Output enable control pin

— Output enable or disable will not cause any runt pulses

▪

C / SPI serial port

— Individual output enables, output type selection and output

power-down control bits supported

— Input mux selection control bit

▪

Core voltage supply of 3.3V, 2.5V or 1.8V

▪

-40°C to +85°C ambient operating temperature

▪

Lead-free (RoHS 6) packaging

December 19, 2016

8P79818 Datasheet

Principles of Operation

Input Selection

The 8P79818 supports two input references: CLK0 and CLK1 that may be driven with differential or single-ended clock signals. Either or both

may be used as the source frequency for either output divider under control of the CLK_SEL input pin or under register control.

The CLK_SEL pin is the default selection mechanism and selects whether both dividers are driven by the CLK0, nCLK0 input (CLK_SEL =

Low) or by the CLK1, nCLK1 input (CLK_SEL = High).

If the user enables register control via the SEL_REG control bit, then there are 4 selection options available as shown in

Table 2.

Table 2: Input Selection Register Control (SEL_REG = 1)

CLK_SEL [1:0]

Description

Divider A & B both driven from CLK0

Divider A driven from CLK1 &

Divider B driven from CLK0

Divider A driven from CLK0 &

Divider B driven from CLK1

Divider A & B both driven from CLK1

Output Dividers

Each bank of outputs has its own divider. All outputs in the same bank will be driven by that divider and so will all have the same frequency.

Divider A supplies the QA output bank and Divider B supplies the QB output bank. Each divider is capable of being driven by the same or a

different input frequency. Each divider can pass that input frequency directly to the outputs or to divide it by any integer from 2 up to 511.

Output Drivers

The QA[0:3] and QB[0:3] clock outputs are provided with register-controlled output drivers. By selecting the output drive type in the appropriate

CML operation supports both a 400mV peak-peak swing and an 800mV peak-peak swing selection.

The operating voltage ranges of each output bank is determined by its independent output power pin (V

CCOA

or V

CCOB

). Output voltage levels

of 1.8V, 2.5V or 3.3V are supported for differential operation and LVCMOS operation. In addition, LVCMOS output operation supports 1.5V

CCO

A global OE input pin is provided. If the OE pin is negated (Low), then all outputs will be in a high-impedance state. If the OE pin is asserted

(High), then each output will behave as indicated by its individual register enable bit. Using the global OE pin to enable or disable outputs will

not result in any ‘runt’ clock pulses on the outputs.

Each output bank may be enabled or disabled using the SYNC_DISx register bit. Using these bits to enable or disable outputs will not result in

any ‘runt’ clock pulses on the outputs.

Individual outputs within a bank may be enabled or disabled using the DIS_Qxm register bits. These bits however may result in ‘runt’ pulses on

the outputs if the output is otherwise enabled, so it is recommended that the entire bank be disabled via the appropriate SYNC_DISx register

bit while an individual output is being enabled using the DIS_Qxm bit to avoid a possible ‘runt’ pulse on the output. If ‘runt’ pulses are not a

concern, then the DIS_Qxm bits may be used directly.

LVCMOS Operation

When a given output is configured to provide LVCMOS levels, then both the Q and nQ outputs will toggle at the selected output frequency. All

the previously described configuration and control apply equally to both outputs. Frequency, voltage levels and enable / disable status apply to

both the Q and nQ pins.

When configured as LVCMOS, the Q & nQ outputs can be selected to be phase-aligned with each other or inverted relative to one another.

Phase-aligned outputs will have increased simultaneous switching currents which can negatively affect phase noise performance and power

consumption. It is recommended that use of this selection be kept to a minimum.

December 19, 2016

8P79818NLGI8 Related Products

	8P79818NLGI8	8P79818NLGI
Description	IC CLOCK BUFFER 32VFQFPN	IC CLOCK BUFFER 32VFQFPN

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