DSC400-3331Q0097
Crystal-less™ Configurable Clock Generator
General Description
The DSC400-3331Q0097 is a four output
crystal-less™ clock generator. It utilizes Microchip's
proven PureSilicon™ MEMS technology to provide
excellent jitter and stability while incorporating
additional device functionality.
The frequencies of the outputs can be identical or
independently derived from two shared PLLs. Each
output may be configured independently to support
LVCMOS, LVPECL, LVDS, or HCSL output
standards.
The DSC400-3331Q0097 provides two independent
select lines for choosing between two sets of pre-
configured frequencies per bank. It also has two OE
pins to allow for enabling and disabling outputs.
Features
• Frequencies and output formats:
- 16MHz LVCMOS x 1
- 50MHz LVDS x 3
• Low RMS phase jitter: <1ps (typ)
• High stability: ±25ppm, ±50ppm
• Wide temperature range
- Ext. commercial: -20°C to +70°C
- Industrial: -40°C to +85°C
• High supply noise rejection: -50dBc
• Available pin-selectable frequency table
- 1 pin per bank for 2 frequency sets
• Excellent shock & vibration immunity
- Qualified to MIL-STD-883
• High reliability
- 20x better MTF than quartz based devices
• Supply range of 2.25V to 3.6V
• AEC-Q100 automotive qualified
• 20-pin 5mm x 3.2mm QFN package
Applications
• Communications and Networks
• Ethernet
- 1G, 10GBASE-T/KR/LR/SR, and FCoE
• Storage Area Networks
- SATA, SAS, Fibre Channel
• Passive Optical Networks
- EPON, 10G-EPON, GPON, 10G-GPON
• HD/SD/SDI Video & Surveillance
• Automotive
• Media and Video
• Embedded and Industrial
Block Diagram
Control Circuitry
Output
Control
And
Dividers
VDD1/VDD2
CLK1
16MHz LVCMOS
CLK4+
50MHz LVDS
CLK4-
CLK3+
50MHz LVDS
CLK3-
CLK2+
50MHz LVDS
CLK2-
VSS
MEMS
OE1
FSB1
PLL
Control Circuitry
Output
Control
And
Dividers
MEMS
OE2
FSB2
PLL
ClockWorks is a registered trademark of Microchip Technology Inc.
Microchip Technology Inc.
http://www.microchip.com
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DSC400-3331Q0097
Ordering Information
Ordering Part Number
DSC400-3331Q0097KE2
DSC400-3331Q0097KE2T
DSC400-3331Q0097KE1
DSC400-3331Q0097KE1T
DSC400-3331Q0097KI2
DSC400-3331Q0097KI2T
DSC400-3331Q0097KI1
DSC400-3331Q0097KI1T
Temperature Range
-20°C to +70°C
-20°C to +70°C
-20°C to +70°C
-20°C to +70°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
High Stability
±25ppm
±25ppm
±50ppm
±50ppm
±25ppm
±25ppm
±50ppm
±50ppm
Shipping
Tube
Tape and Reel
Tube
Tape and Reel
Tube
Tape and Reel
Tube
Tape and Reel
Package
20-pin 5mm x 3.2mm QFN
20-pin 5mm x 3.2mm QFN
20-pin 5mm x 3.2mm QFN
20-pin 5mm x 3.2mm QFN
20-pin 5mm x 3.2mm QFN
20-pin 5mm x 3.2mm QFN
20-pin 5mm x 3.2mm QFN
20-pin 5mm x 3.2mm QFN
Devices are Green and RoHS compliant. Sample material may have only a partial top mark.
Pin Configuration
CLK4+
CLK3+
CLK4-
CLK3-
VDD1
FSB1
OE1
NC
VSS
VSS
VSS
VSS
NC
OE2
CLK2+
CLK2-
CLK1
VDD2
20-pin 5mm x 3.2mm QFN
April 27, 2017
5189
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FSB2
NC
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DSC400-3331Q0097
Pin Description
Pin Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Pin Name
OE1
NC
VSS
VSS
NC
CLK1
CLK2-
CLK2+
VDD2
FSB2
OE2
NC
VSS
VSS
CLK3-
CLK3+
CLK4-
CLK4+
VDD1
FSB1
PWR
PWR
O
O
O
O
PWR
I
O
O
O
PWR
I
I
PWR
PWR
Pin Type
I
Pin Function
Output enable for Bank 1 (CLK1 and CLK4); active high - see Table 1
Leave unconnected or connect to ground
Ground
Ground
Leave unconnected or connect to ground
LVCMOS output 1 = 16MHz
Complement output of differential pair 2
True output of differential pair 2
Power supply for Bank 2 (CLK3 and CLK2)
Input for selecting pre-configured frequencies on Bank 2 (CLK3 and CLK2)
No connect if the function is not used.
Output enable for Bank 2 (CLK3 and CLK2); active high - see Table 1
Leave unconnected or connect to ground
Ground
Ground
Complement output of differential pair 3
True output of differential pair 3
Complement output of differential pair 4
True output of differential pair 4
Power supply for Bank 1 (CLK1 and CLK4)
Input for selecting pre-configured frequencies on Bank 1 (CLK1 and CLK4)
No connect if the function is not used.
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DSC400-3331Q0097
Operational Description
The DSC400-3331Q0097 is a crystal-less™ clock generator. Unlike older clock generators in the industry, it does not require an
external crystal to operate; it relies on integrated MEMS resonators that interface with internal PLLs. This technology enhances
performance and reliability by allowing tighter frequency stability over a far wider temperature range. In addition, the higher
resistance to shock and vibration decreases the aging rate, greatly improving product life in the system.
Inputs
There are 4 input signals in the device. Each has an internal (40kOhms) pull up, which defaults the selection to a high (1). Inputs
can be controlled through hardware strapping method with a resistor to ground to assert the input low (0). Inputs may also be
controlled by other components' GPIOs. In case more than one frequency set is desired, FSB1 and FSB2 are used for independent-
ly selecting one of two sets frequency per bank. FSB1 selects the pre-configured frequency set on Bank 1 (CLK1 and CLK4) and
FSB2 selects the pre-configured frequency set on Bank 2 (CLK3 and CLK2). If there is a requirement to disable outputs, the
inputs OE1 and OE2 are used to disable the banks of outputs. Outputs are disabled in tristate (Hi-Z) mode, see Table 1 below.
OE1
0
0
1
1
OE2
0
1
0
1
Bank 1 (CLK1 and CLK4)
Hi-Z
Hi-Z
Running
Running
Table 1. Output Enable (OE) Selection Table
Bank 2 (CLK3 and CLK2)
Hi-Z
Running
Hi-Z
Running
Outputs
The four outputs are grouped into two banks. Each bank is supplied by an independent VDD to allow for optimized noise
isolation between the two banks. Each bank provides two synchronous outputs generated by a common PLL:
• Bank 1 is composed of outputs CLK1 and CLK4
• Bank 2 is composed of outputs CLK3 and CLK2
Each output maybe pre-configured independently to be one of the following formats: LVCMOS, LVDS, LVPECL or HCSL.
In case the output is configured to be single ended (LVCMOS only), the frequency is generated on the true output (CLKx+) and
the complement output (CLKx-) is shut off in a low state. Frequencies can be chosen from 2.3MHz to 460MHz for differential
outputs and from 2.3MHz to 170MHz on LVCMOS outputs.
Output Clock Frequencies
Output
Frequency (MHz)
CLK1
16
CLK2
50
CLK3
50
CLK4
50
Power
VDD1 and VDD2 supply the power to banks 1 and 2 respectively. Each VDD may have different supply voltage from the other
as long as it is within the 2.25V to 3.6V range. Each VDD pin should have a 0.1µF capacitor to filter high frequency noise.
VSS is common to the entire device. The exposed die paddle should be connected to VSS.
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DSC400-3331Q0097
Absolute Maximum Ratings
Item
Supply Voltage
Input Voltage
Junction Temp
Storage Temp
Soldering Temp
ESD
HBM
MM
CDM
1000+ years of data retension on internal memory
Min.
-0.3
-0.3
-
-55
-
Max.
+4.0
VDD + 0.3
+150
+150
+260
4000
400
1500
Units
V
V
°C
°C
°C
Condition
40sec max.
-
V
Specifications
(Unless specified otherwise: Ta = 25°C, VDD = 3.3V)
Parameter
Supply Voltage¹
Supply Current - Core²
Frequency Stability
Aging - first year
Aging - after first year
Startup Time³
Input Logic Levels
Input Logic High
Input Logic Low
Output Disable Time
Output Enable Time
4
Pull-Up Resistor
4
Symbol
VDD
IDDcore
F
Fy1
Fy2
+
tSU
VIH
VIL
tDA
tEN
Rpu
Condition
Min.
2.25
Typ.
Max.
3.6
Unit
V
mA
ppm
ppm
ppm
ms
V
ns
ns
kOhms
OE (1:2) = 0
All outputs are disabled
All temp and VDD ranges
1 year @ 25°C
Year 2 and beyond @ 25°C
T = 25°C
0.75 x VDD
-
OE(1:2) transition from 1 to 0
OE(1:2) transition from 0 to 1
All input pins have an internal pull-up
40
44
±25
±50
±5
< ±1/yr
5
-
0.25 x VDD
5
20
40
Notes:
1. VDD pins should be filtered with 0.1µF capacitor connected between VDD and VSS.
2. The addition of IDDcore and IDDio provides total current consumption of the device.
3. tSU is time to 100ppm stable output frequency after VDD is applied and outputs are enabled.
4. Output Waveform figures below the parameters. See Output Waveform section.
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