DSC2011FI1-E0012
Crystal-less™ Configurable Clock Generator
General Description
The DSC2011FI1-E0012 is a programmable, high
performance dual LVCMOS output oscillator utilizing
Micrel's proven silicon MEMS technology to provide
excellent jitter and stability while incorporating
additional device functionality. Two LVCMOS outputs
are controlled by separate supply voltages to allow for
independent voltage level control. The frequencies of
the outrputs can be identical or independently derived
from a common PLL frequency source.
The DSC2011FI1-E0012 has provision for up to eight
user-defined pre-programmed, pin-selectable output
frequency combinations. The DSC2011FI1-E0012 is
also equipped with independent pin-selectable output
drive strengths to reduce EMI and noise.
Features
• Frequency and output formats:
- LVCMOS
154/65/71/108/119/130.25/148.5/162MHz
- LVCMOS
154/65/71/108/119/130.25/148.5/162MHz
• Low RMS phase jitter: <1ps (typ)
• ±50ppm frequency stability
• -40°C to +85°C industrial temperature range
• High supply noise rejection: -50dBc
• Pin-selectable configurations
- 2-bit output drive strength
- Up to 8 output frequency combinations
• Excellent shock & vibration immunity
- Qualified to MIL-STD-883
• High reliability
- 20x better MTF than quartz oscillators
• Supply range of 2.25 to 3.6V
• AEC-Q100 automotive qualified
• 14-pin 3.2mm x 2.5mm QFN package
Applications
• Consumer Electronics
• Storage Area Networks
- SATA, SAS, Fibre Channel
• Passive Optical Networks
- EPON, 10G-EPON, GPON, 10G-GPON
• Ethernet
- 1G, 10GBASE-T/KR/LR/SR, and FCoE
• HD/SD/SDI Video & Surveillance
• PCI Express
• Automotive
VDD/VDD2
Block Diagram
O1S0/O1S1
CLK1
154MHz LVCMOS
Control Circuitry
÷2
÷ M1
MEMS
PLL
÷2
FS0/FS1/FS2
OE
÷ M2
CLK2
154MHz LVCMOS
O2S0/O2S1
VSS
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 •
http://www.micrel.com
October 10, 2014
2441
Revision 1.0
tcghelp@micrel.com
or (408) 955-1690
Micrel, Inc.
DSC2011FI1-E0012
Ordering Information
Ordering Part Number
DSC2011FI1-E0012
DSC2011FI1-E0012T
Industrial Temperature Range
-40°C to +85°C
-40°C to +85°C
Shipping
Tube
Tape and Reel
Package
14-pin 3.2mm x 2.5mm QFN
14-pin 3.2mm x 2.5mm QFN
Devices are Green and RoHS compliant. Sample material may have only a partial top mark.
OE
NC
O2S0
GND
VDD2
O2S1
VDD
Pin Configuration
CLK2
O1S1
O1S0
CLK1
FS0
FS1
Pin Description
Pin Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Pin Name
OE
NC
O2S0
GND
FS0
FS1
FS2
CLK1
O1S0
O1S1
CLK2
VDD2
VDD
O2S1
I
PWR
I
I
I
O
I
I
O
PWR
PWR
I
Pin Type
I
14-pin 3.2mm x 2.5mm QFN
FS2
Pin Function
Enables outputs when high and disables outputs when low
Leave unconnected or connect to ground
Least significant bit for drive strength selection for CLK2, see Table 1 for details
Ground
Least significant bit for frequency selection, see Table 2 for details
Middle bit for frequency selection, see Table 2 for details
Most significant bit for frequency selection, see Table 2 for details
LVCMOS output
Least significant bit for drive strength selection for CLK1, see Table 1 for details
Most significant bit for drive strength selection for CLK1, see Table 1 for details
LVCMOS output
Power supply for LVCMOS output CLK2
Power supply
Most significant bit for drive strength selection for CLK2, see Table 1 for details
October 10, 2014
2441
2
Revision 1.0
tcghelp@micrel.com
or (408) 955-1690
Micrel, Inc.
DSC2011FI1-E0012
Operational Description
The DSC2011FI1-E0012 is a dual output LVCMOS
oscillator consisting of a MEMS resonator and a
supporting PLL IC. The two LVCMOS outputs
are generated through independent 8-bit programmable
dividers from the output of the internal PLL. The two
constraints are imposed on the output frequencies:
1) f2 = M x f1/N, where M and N are even integers
between 4 and 254, 2) 1.2GHz < N x f2 < 1.7GHz.
The actual frequencies output by DSC2011FI1-E0012
are controlled by an internal pre-programmed memory
(OTP). This memory stores all coefficients required by
the PLL for up to eight different frequency combinations.
Three control pins (FS0 - FS2) select the output frequency
combination.
DSC2011FI1-E0012 has independent control of the output
voltage levels of the two outputs. The high voltage level of
CLK1 is equal to the main supply voltage, VDD (pin 13).
VDD2 (pin 12) sets the high voltage level of CLK2.
VDD2 must be equal to or less than VDD at all times to
insure proper operation. VDD2 can be as low as 1.65V.
When OE (pin 1) is floated or connected to VDD, the
DSC2011FI1-E0012 is in operational mode. Driving
Enable to ground will tri-state both output drivers
(hi-impedance mode).
DSC2011FI1-E0012 has programmable output drive
strength for each output. Using two control pins (OXS0-
OXS1) for each output, the drive strength can be indepen-
dently adjusted to match circuit board impedances to
reduce spower supply noise, overshoot/undershoot and
EMI. Table 1 displays typical rise / fall times for the
output with a 15pF load capacitance as a function of
these control pins at VDD = 3.3V and room temperature.
Output Drive Strength Bits [OXS1, OXS0] - Default is [11]
00
tr (ns)
tf (ns)
1.6
2.4
01
1.4
2.2
Table 1. Rise/Fall Times for Drive Strengths
10
1.2
1.5
11
1.1
1.4
Output Clock Frequencies
Frequency select bits are weakly tied high so if left unconnected the default setting will be [111] and the device will output the
associated frequency highlighted in bold.
Freq Select Bits [FS2, FS1, FS0] - Default is [111]
Freq (MHz)
000
CLK1
CLK2
65
65
001
71
71
010
108
108
011
119
119
100
130.25
130.25
101
148.5
148.5
110
162
162
111
154
154
Table 2. Pin-Selectable Output Frequencies
Absolute Maximum Ratings
Item
Supply Voltage
Input Voltage
Junction Temp
Storage Temp
Soldering Temp
ESD
HBM
MM
CDM
1000+ years of data retention on internal memory
Min.
-0.3
-0.3
-
-55
-
Max.
+4.0
VDD + 0.3
+150
+150
+260
4000
400
1500
Units
V
V
°C
°C
°C
Condition
40sec max.
-
V
October 10, 2014
2441
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Revision 1.0
tcghelp@micrel.com
or (408) 955-1690
Micrel, Inc.
DSC2011FI1-E0012
Specifications
(Unless specified otherwise: T = 25°C, max LVCMOS drive strength)
Parameter
Supply Voltage¹
Supply Current
Supply Current²
Frequency Stability
Aging
Startup Time³
Input Logic Levels
Input Logic High
Input Logic Low
Output Disable Time
4
Output Enable Time
Pull-Up Resistor²
Symbol
VDD
IDD
IDD
F
F
tSU
VIH
VIL
tDA
tEN
Pull-up exists on all digital IO
LVCMOS Outputs
Output Logic Levels
Output Logic High
Output Logic Low
Output Transition Time
4
Rise Time
Fall Time
Frequency
Output Duty Cycle
Period Jitter
5
Condition
Min.
2.25
Typ.
Max.
3.6
Units
V
mA
mA
OE pin low - outputs are disabled
OE pin high - outputs are enabled
CL = 15pF, F01 = F02 = 125MHz
Includes frequency variation due to initial
tolerance, temp. and power supply voltage
First year (@ 25°C)
T = 25°C
0.75 x VDD
-
21
32
23
±50
±5
5
-
0.25 x VDD
5
20
40
ppm
ppm
ms
V
ns
ns
kOhms
VOH
VOL
tR
tF
CLK1
CLK2
SYM
JPER
JPH
I = ±6mA
0.9 x VDD
-
1.1
1.4
154
154
45
-
0.1 x VDD
2
2
V
20% to 80%
CL = 15pF
[FS2, FS1, FS0] = [1, 1, 1]
ns
MHz
55
3
0.3
0.38
1.7
%
psRMS
psRMS
F01 = F02 = 125MHz
200kHz to 20MHz @ 125MHz
100kHz to 20MHz @ 125MHz
12kHz to 20MHz @ 125MHz
Integrated Phase Noise
2
Notes:
1. Pin 12 VDD2, and pin 13 VDD should be filtered with 0.1uF capacitors.
2. Output is enabled if OE pin is floated or not connected.
3. tSU is time to 100ppm stable output frequency after VDD is applied and outputs are enabled.
4. Output Waveform and Test Circuit figures below define the parameters.
5. Period Jitter includes crosstalk from adjacent output.
October 10, 2014
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tcghelp@micrel.com
or (408) 955-1690
Micrel, Inc.
DSC2011FI1-E0012
Nominal Performance Parameters
(Unless specified otherwise: T = 25°C, VDD = 3.3V)
Figure 1. LVCMOS Phase Jitter (integrated phase noise)
LVCMOS Output Waveform
Output
OE
Figure 2. LVCMOS Output Waveform
MSL 1 @ 260°C refer to JSTD-020C
Ramp-Up Rate (200°C to Peak Temp)
Preheat Time 150°C to 200°C
Time maintained above 217°C
Peak Temperature
Time within 5°C of actual Peak
Ramp-Down Rate
Time 25°C to Peak Temperature
3°C/sec Max.
60 - 180 sec
60 - 150 sec
255 - 260°C
20 - 40 sec
6°C/sec Max.
8 min Max.
October 10, 2014
2441
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or (408) 955-1690
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