DSC2033FI2-F0022
Crystal-less™ Configurable Clock Generator
General Description
The DSC2033FI2-F0022 is a programmable, high
performance dual LVDS output oscillator utilizing
Micrel's proven silicon MEMS technology to provide
excellent jitter and stability while incorporating
additional device functionality. Two LVDS outputs
are controlled by separate supply voltages to allow for
high output isolation. The frequencies of the outrputs
can be identical or independently derived from a
common PLL frequency source.
The DSC2033FI2-F0022 has provision for up to eight
user-defined pre-programmed, pin-selectable output
frequency combinations.
Features
• Frequency and output formats:
- LVDS
100MHz
- LVDS
100MHz
• Low RMS phase jitter: <1ps (typ)
• ±25ppm frequency stability
• -40°C to +85°C industrial temperature range
• High supply noise rejection: -50dBc
• Pin-selectable configurations
- Up to 8 output frequency combinations
• Excellent shock & vibration immunity
- Qualified to MIL-STD-883
• High reliability
- 20x better MTF than quartz oscillators
• Supply range of 2.25 to 3.6V
• AEC-Q100 automotive qualified
• 14-pin 3.2mm x 2.5mm QFN package
Applications
• Consumer Electronics
• Storage Area Networks
- SATA, SAS, Fibre Channel
• Passive Optical Networks
- EPON, 10G-EPON, GPON, 10G-GPON
• Ethernet
- 1G, 10GBASE-T/KR/LR/SR, and FCoE
• HD/SD/SDI Video & Surveillance
• PCI Express
• Automotive
VDD/VDD2
Block Diagram
CLK1+
100MHz LVDS
CLK1-
Control Circuitry
÷2
÷ M1
MEMS
PLL
CLK2+
100MHz LVDS
CLK2-
÷2
FS0/FS1/FS2
OE
÷ M2
VSS
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 •
http://www.micrel.com
November 06, 2015
3359
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tcghelp@micrel.com
or (408) 955-1690
Micrel, Inc.
DSC2033FI2-F0022
Ordering Information
Ordering Part Number
DSC2033FI2-F0022
DSC2033FI2-F0022T
Industrial Temperature Range
-40°C to +85°C
-40°C to +85°C
Shipping
Tube
Tape and Reel
Package
14-pin 3.2mm x 2.5mm QFN
14-pin 3.2mm x 2.5mm QFN
Devices are Green and RoHS compliant. Sample material may have only a partial top mark.
OE
NC
NC
GND
VDD2
VDD
Pin Configuration
NC
CLK2+
CLK2-
CLK1-
CLK1+
FS0
FS1
14-pin 3.2mm x 2.5mm QFN
Pin Description
Pin Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Pin Name
OE
NC
NC
GND
FS0
FS1
FS2
CLK1+
CLK1-
CLK2-
CLK2+
VDD2
VDD
NC
PWR
I
I
I
O
O
O
O
PWR
PWR
Pin Type
I
Pin Function
Enables outputs when high and disables outputs when low
Leave unconnected or connect to ground
Leave unconnected or connect to ground
Ground
Least significant bit for frequency selection, see Table 1 for details
Middle bit for frequency selection, see Table 1 for details
Most significant bit for frequency selection, see Table 1 for details
Positive LVDS output
Negative LVDS output
Negative LVDS output
Positive LVDS output
Power supply for LVDS output CLK2, 1.65V to 3.6V (VDD2
≤
VDD)
Power supply
Leave unconnected or connect to ground
November 06, 2015
3359
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FS2
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Micrel, Inc.
DSC2033FI2-F0022
Operational Description
The DSC2033FI2-F0022 is a dual output LVDS
oscillator consisting of a MEMS resonator and a
supporting PLL IC. The two LVDS outputs are
generated through independent 8-bit programmable
dividers from the output of the internal PLL. The
two constraints are imposed on the output frequencies:
1) f2 = M x f1/N, where M and N are even integers
between 4 and 254, 2) 1.2GHz < N x f2 < 1.7GHz.
The actual frequencies output by DSC2033FI2-F0022
are controlled by an internal pre-programmed memory
(OTP). This memory stores all coefficients required
by the PLL for up to eight different frequency
combinations. Three control pins (FS0 - FS2) select
the output frequency combination.
When OE (pin 1) is floated or connected to VDD,
the DSC2033 is in operational mode. Driving OE
to ground will tri-state both output drivers (hi-
impedance mode).
Output Clock Frequencies
Frequency select bits are weakly tied high so if left unconnected the default setting will be [111] and the device will output the
associated frequency highlighted in bold.
Freq Select Bits [FS2, FS1, FS0] - Default is [111]
Freq (MHz)
000
CLK1
CLK2
NA
NA
001
NA
NA
010
NA
NA
011
NA
NA
100
NA
NA
101
NA
NA
110
NA
NA
111
100
100
Table 1. Pin-Selectable Output Frequencies
Absolute Maximum Ratings
Item
Supply Voltage
Input Voltage
Junction Temp
Storage Temp
Soldering Temp
ESD
HBM
MM
CDM
1000+ years of data retention on internal memory
Min.
-0.3
-0.3
-
-55
-
Max.
+4.0
VDD + 0.3
+150
+150
+260
4000
400
1500
Units
V
V
°C
°C
°C
Condition
40sec max.
-
V
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DSC2033FI2-F0022
Specifications
(Unless specified otherwise: T = 25°C)
Parameter
Supply Voltage¹
Supply Current
Supply Current²
Frequency Stability
Aging
Startup Time³
Input Logic Levels
Input Logic High
Input Logic Low
Output Disable Time
Output Enable Time
Pull-Up Resistor²
4
Symbol
VDD
IDD
IDD
F
F
tSU
VIH
VIL
tDA
tEN
Condition
Min.
2.25
Typ.
Max.
3.6
Units
V
mA
mA
OE pin low - output is disabled
OE pin high - outputs are enabled
RL = 50Ohms, F01 = F02 = 156.25MHz
Includes frequency variation due to initial
tolerance, temp. and power supply voltage
First year (@ 25°C)
T = 25°C
0.75 x VDD
-
21
38
23
±25
±5
5
-
0.25 x VDD
5
20
ppm
ppm
ms
V
ns
ns
kOhms
Pull-up exists on all digital IO
LVDS Outputs
40
Output Offset Voltage
Delta Offset Voltage
Pk to Pk Output Swing
Output Transition Time
Rise Time
Fall Time
Frequency
Output Duty Cycle
Period Jitter
5
Integrated Phase Noise
4
RL = 100Ohms Differential
1.125
1.4
50
V
mV
mV
ps
Single-Ended
tR
tF
CLK1
CLK2
SYM
JPER
JPH
20% to 80%
RL = 50Ohms, CL = 2pF (to GND)
[FS2, FS1, FS0] = [1, 1, 1]
Differential
F01 = F02 = 156.25MHz
200kHz to 20MHz @ 156.25MHz
100kHz to 20MHz @ 156.25MHz
12kHz to 20MHz @ 156.25MHz
48
350
200
100
100
350
MHz
52
%
psRMS
2.5
0.28
0.4
1.7
2
psRMS
Notes:
1. Pin 12 VDD2, and pin 13 VDD should be filtered with 0.1uF capacitors.
2. Output is enabled if OE pin is floated or not connected.
3. tSU is time to 100ppm stable output frequency after VDD is applied and outputs are enabled.
4. Output Waveform and Test Circuit figures below define the parameters.
5. Period Jitter includes crosstalk from adjacent output.
November 06, 2015
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DSC2033FI2-F0022
Nominal Performance Parameters
(Unless specified otherwise: T = 25°C, VDD = 3.3V)
Figure 1. LVDS Phase Jitter (integrated phase noise)
LVDS Output Waveform
350
OE
Figure 2. LVDS Output Waveform
MSL 1 @ 260°C refer to JSTD-020C
Ramp-Up Rate (200°C to Peak Temp)
Preheat Time 150°C to 200°C
Time maintained above 217°C
Peak Temperature
Time within 5°C of actual Peak
Ramp-Down Rate
Time 25°C to Peak Temperature
3°C/sec Max.
60 - 180 sec
60 - 150 sec
255 - 260°C
20 - 40 sec
6°C/sec Max.
8 min Max.
November 06, 2015
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