DSC2010FI2-B0014
Crystal-less™ Configurable Clock Generator
General Description
The DSC2010FI2-B0014 is a high performance
LVCMOS oscillator utilizing Micrel's proven silicon
MEMS technology to provide excellent jitter and
stability while incorporating additional device
functionality.
The DSC2010FI2-B0014 allows the user to easily
modify the frequency and drive strength of the
oscillator using pins.
The DSC2010FI2-B0014 has provision for up to four
user-defined pre-programmed, pin-selectable output
frequencies, and eight pin-selectable output drive
levels to help reduce EMI.
Features
• Frequency and output formats:
- LVCMOS
27/27/26.973/27MHz
• Low RMS phase jitter: <1ps (typ)
• ±25ppm frequency stability
• -40°C to +85°C industrial temperature range
• High supply noise rejection: -50dBc
• Pin-selectable configurations
- 3-bit output drive strength
- Up to 4 output frequency combinations
• Excellent shock & vibration immunity
- Qualified to MIL-STD-883
• High reliability
- 20x better MTF than quartz oscillators
• Supply range of 2.25 to 3.6V
• AEC-Q100 automotive qualified
• 14-pin 3.2mm x 2.5mm QFN package
Applications
• Consumer Electronics
• Storage Area Networks
- SATA, SAS, Fibre Channel
• Passive Optical Networks
- EPON, 10G-EPON, GPON, 10G-GPON
• Ethernet
- 1G, 10GBASE-T/KR/LR/SR, and FCoE
• HD/SD/SDI Video & Surveillance
• PCI Express
• Automotive
Block Diagram
VDD/VDD2
Control Circuitry
OS0/OS1/OS2
MEMS
PLL
÷2
÷ M1
CLK1
27MHz LVCMOS
FS0/FS1
OE
VSS
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 •
http://www.micrel.com
February 02, 2016
3478
Revision 1.0
tcghelp@micrel.com
or (408) 955-1690
Micrel, Inc.
DSC2010FI2-B0014
Ordering Information
Ordering Part Number
DSC2010FI2-B0014
DSC2010FI2-B0014T
Industrial Temperature Range
-40°C to +85°C
-40°C to +85°C
Shipping
Tube
Tape and Reel
Package
14-pin 3.2mm x 2.5mm QFN
14-pin 3.2mm x 2.5mm QFN
Devices are Green and RoHS compliant. Sample material may have only a partial top mark.
OE
NC
NC
GND
VDD2
VDD
OS2
Pin Configuration
NC
OS1
OS0
CLK1
FS0
FS1
14-pin 3.2mm x 2.5mm QFN
Pin Description
Pin Number
1
2
3
4
5
6
7
8
9
10
11
12, 13
14
Pin Name
OE
NC
NC
GND
FS0
FS1
NC
CLK1
OS0
OS1
NC
VDD2, VDD
OS2
PWR
I
O
I
I
PWR
I
I
Pin Type
I
Pin Function
Enables outputs when high and disables outputs when low
Leave unconnected or connect to ground
Leave unconnected or connect to ground
Ground
Least significant bit for frequency selection, see Table 2 for details
Most significant bit for frequency selection, see Table 2 for details
Leave unconnected or connect to ground
LVCMOS output
Least significant bit for output drive strength selection, see Table 1 for details
Middle bit for output drive strength selection, see Table 1 for details
Leave unconnected or connect to ground
Power supply
Most significant bit for output drive strength selection, see Table 1 for details
February 02, 2016
3478
2
NC
Revision 1.0
tcghelp@micrel.com
or (408) 955-1690
Micrel, Inc.
DSC2010FI2-B0014
Operational Description
The DSC2010FI2-B0014 is a LVCMOS oscillator
consisting of a MEMS resonator and a supporting
PLL IC. The LVCMOS output is generated through
independent 8-bit programmable dividers from the
output of the internal PLL.
The actual frequency output by DSC2010FI2-B0014
is controlled by an internal pre-programmed memory
(OTP). This memory stores all coefficients required
by the PLL for up to four different frequencies.
Two control pins (FS0, FS1) select the output
frequency.
When OE (pin 1) is floated or connected to VDD, the
DSC2010FI2-B0014 is in operational mode. Driving
OE to ground will disable the output driver (hi-
impedance mode).
DSC2010FI2-B0014 has programmable output drive
strength. Using three control pins (OS0-OS2) the drive
strength can be adjusted to match circuit board
impedances to reduce power supply noise, overshoot/
undershoot and EMI. Table 1 displays typical rise / fall
times for the output with a 15pF load capacitance as a
function of these control pins at VDD = 3.3V and
room temperature.
Output Drive Strength Bits [OS2, OS1, OS0] - Default is [111]
000
tr (ns)
tf (ns)
2.1
2.5
001
1.7
2.4
010
1.6
2.4
011
1.4
2.2
100
1.3
1.8
101
1.3
1.6
110
1.2
1.4
111
1.1
1.4
Table 1. Rise/Fall Times for Drive Strengths
Output Clock Frequencies
Frequency select bits are weakly tied high so if left unconnected the default setting will be [11] and the device will output the
associated frequency highlighted in bold.
Freq Select Bits [FS1, FS0] - Default is [11]
Freq (MHz)
00
CLK1
27
01
26.973
Table 2. Pin-Selectable Output Frequencies
10
27
11
27
Absolute Maximum Ratings
Item
Supply Voltage
Input Voltage
Junction Temp
Storage Temp
Soldering Temp
ESD
HBM
MM
CDM
1000+ years of data retention on internal memory
Min.
-0.3
-0.3
-
-55
-
Max.
+4.0
VDD + 0.3
+150
+150
+260
4000
400
1500
Units
V
V
°C
°C
°C
Condition
40sec max.
-
V
February 02, 2016
3478
3
Revision 1.0
tcghelp@micrel.com
or (408) 955-1690
Micrel, Inc.
DSC2010FI2-B0014
Specifications
(Unless specified otherwise: T = 25°C, max LVCMOS drive strength)
Parameter
Supply Voltage¹
Supply Current
Frequency Stability
Aging
Startup Time²
Input Logic Levels
Input Logic High
Input Logic Low
Output Disable Time³
Output Enable Time³
Pull-Up Resistor
4
Symbol
VDD
IDD
F
F
tSU
VIH
VIL
tDA
tEN
Pull-up exists on all digital IO
LVCMOS Output
Supply Current
4
Output Logic Levels
Output Logic High
Output Logic Low
Output Transition Time³
Rise Time
Fall Time
Frequency
Output Duty Cycle
Period Jitter
Integrated Phase Noise
IDD
OE pin high - output is enabled
CL = 15pF, F0 = 125MHz
I = ±6mA
0.9 x VDD
-
1.1
1.3
27
45
F0 = 125MHz
200kHz to 20MHz @ 125MHz
100kHz to 20MHz @ 125MHz
12kHz to 20MHz @ 125MHz
3
0.3
0.38
1.7
55
31
35
mA
40
OE pin low - output is disabled
Includes frequency variation due to initial
tolerance, temp. and power supply voltage
First year (@ 25°C)
T = 25°C
0.75 x VDD
-
Condition
Min.
2.25
21
Typ.
Max.
3.6
23
±25
±5
5
-
0.25 x VDD
5
20
Units
V
mA
ppm
ppm
ms
V
ns
ns
kOhms
VOH
VOL
tR
tF
CLK1
SYM
JPER
JPH
-
0.1 x VDD
2
2
V
20% to 80%
CL = 15pF
[FS1, FS0] = [1, 1]
ns
MHz
%
psRMS
2
psRMS
Notes:
1. Pin 12 VDD2, and pin 13 VDD should be filtered with 0.1uF capacitors.
2. tSU is time to 100ppm stable output frequency after VDD is applied and outputs are enabled.
3. Output Waveform and Test Circuit figures below define the parameters.
4. Output is enabled if OE pin is floated or not connected.
February 02, 2016
3478
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Revision 1.0
tcghelp@micrel.com
or (408) 955-1690
Micrel, Inc.
DSC2010FI2-B0014
Nominal Performance Parameters
(Unless specified otherwise: T = 25°C, VDD = 3.3V)
Figure 1. LVCMOS Phase Jitter (integrated phase noise)
LVCMOS Output Waveform
Output
OE
Figure 2. LVCMOS Output Waveform
MSL 1 @ 260°C refer to JSTD-020C
Ramp-Up Rate (200°C to Peak Temp)
Preheat Time 150°C to 200°C
Time maintained above 217°C
Peak Temperature
Time within 5°C of actual Peak
Ramp-Down Rate
Time 25°C to Peak Temperature
3°C/sec Max.
60 - 180 sec
60 - 150 sec
255 - 260°C
20 - 40 sec
6°C/sec Max.
8 min Max.
February 02, 2016
3478
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Revision 1.0
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or (408) 955-1690
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