DSC2030FE5-B0018
Crystal-less™ Configurable Clock Generator
General Description
The DSC2030FE5-B0018 is a high performance
LVDS oscillator utilizing Microchip's proven silicon
MEMS technology to provide excellent jitter and
stability while incorporating additional device
functionality.
The DSC2030FE5-B0018 allows the user to easily
modify the frequency of the oscillators using FS pins.
The DSC2030FE5-B0018 has provision for up to four
user-defined pre-programmed, pin-selectable output
frequencies.
Features
• Frequency and output formats:
- LVDS
100/25/50/74.25MHz
• Low RMS phase jitter: <1ps (typ)
• ±10ppm frequency stability
• -20°C to +70°C ext. commercial temperature range
• High supply noise rejection: -50dBc
• 4 Pin-selectable output frequencies
• Excellent shock & vibration immunity
- Qualified to MIL-STD-883
• High reliability
- 20x better MTF than quartz oscillators
• Supply range of 2.25 to 3.6V
• AEC-Q100 automotive qualified
• 14-pin 3.2mm x 2.5mm QFN package
Applications
• Consumer Electronics
• Storage Area Networks
- SATA, SAS, Fibre Channel
• Passive Optical Networks
- EPON, 10G-EPON, GPON, 10G-GPON
• Ethernet
- 1G, 10GBASE-T/KR/LR/SR, and FCoE
• HD/SD/SDI Video & Surveillance
• PCI Express
• Automotive
Block Diagram
VDD/VDD2
Control Circuitry
CLK1+
MEMS
PLL
÷2
÷ M1
CLK1-
100MHz LVDS
FS0/FS1
OE
ClockWorks is a registered trademark of Microchip Technology Inc.
Microchip Technology Inc.
VSS
http://www.microchip.com
February 28, 2017
4944
Revision 1.0
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Microchip Technology Inc.
DSC2030FE5-B0018
Ordering Information
Ordering Part Number
DSC2030FE5-B0018
DSC2030FE5-B0018T
Industrial Temperature Range
-20°C to +70°C
-20°C to +70°C
Shipping
Tube
Tape and Reel
Package
14-pin 3.2mm x 2.5mm QFN
14-pin 3.2mm x 2.5mm QFN
Devices are Green and RoHS compliant. Sample material may have only a partial top mark.
OE
NC
NC
GND
VDD2
VDD
Pin Configuration
NC
NC
NC
CLK1-
CLK1+
FS0
FS1
14-pin 3.2mm x 2.5mm QFN
Pin Description
Pin Number
1
2
3
4
5
6
7
8
9
10
11
12, 13
14
Pin Name
OE
NC
NC
GND
FS0
FS1
NC
CLK1+
CLK1-
NC
NC
VDD2, VDD
NC
PWR
O
O
PWR
I
I
Pin Type
I
Pin Function
Enables outputs when high and disables outputs when low
Leave unconnected or connect to ground
Leave unconnected or connect to ground
Ground
Least significant bit for frequency selection, see Table 1 for details
Most significant bit for frequency selection, see Table 1 for details
Leave unconnected or connect to ground
Positive LVDS output
Negative LVDS output
Leave unconnected or connect to ground
Leave unconnected or connect to ground
Power supply
Leave unconnected or connect to ground
February 28, 2017
4944
2
NC
Revision 1.0
tcghelp@microchip.com
Microchip Technology Inc.
DSC2030FE5-B0018
Operational Description
The DSC2030FE5-B0018 is a LVDS oscillator
consisting of a MEMS resonator and a supporting
PLL IC. The LVDS output is generated through
independent 8-bit programmable dividers from the
output of the internal PLL.
The actual frequency output by DSC2030FE5-B0018
is controlled by an internal pre-programmed memory
(OTP). This memory stores all coefficients required
by the PLL for up to four different frequencies.
Two control pins (FS0, FS1) select the output
frequency.
When OE (pin 1) is floated or connected to VDD,
the DSC2030FE5-B0018 is in operational mode.
Driving OE to ground will tri-state output driver
(hi-impedance mode).
Output Clock Frequencies
Frequency select bits are weakly tied high so if left unconnected the default setting will be [11] and the device will output the
associated frequency highlighted in bold.
Freq Select Bits [FS1, FS0] - Default is [11]
Freq (MHz)
00
CLK1
25
01
50
Table 1. Pin-Selectable Output Frequencies
10
74.25
11
100
Absolute Maximum Ratings
Item
Supply Voltage
Input Voltage
Junction Temp
Storage Temp
Soldering Temp
ESD
HBM
MM
CDM
1000+ years of data retention on internal memory
Min.
-0.3
-0.3
-
-55
-
Max.
+4.0
VDD + 0.3
+150
+150
+260
4000
400
1500
Units
V
V
°C
°C
°C
Condition
40sec max.
-
V
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DSC2030FE5-B0018
Specifications
(Unless specified otherwise: T = 25°C)
Parameter
Supply Voltage¹
Supply Current
Supply Current²
Frequency Stability
Aging
Startup Time³
Input Logic Levels
Input Logic High
Input Logic Low
Output Disable Time
Output Enable Time
Pull-Up Resistor²
4
Symbol
VDD
IDD
IDD
F
F
tSU
VIH
VIL
tDA
tEN
Condition
Min.
2.25
Typ.
Max.
3.6
Units
V
mA
mA
ppm
ppm
ms
V
ns
ns
kOhms
OE pin low - output is disabled
OE pin high - output is enabled
RL = 100Ohms, F0 = 156.25MHz
Includes frequency variation due to initial
tolerance, temp. and power supply voltage
First year (@ 25°C)
T = 25°C
0.75 x VDD
-
21
29
23
32
±10
±5
5
-
0.25 x VDD
5
20
Pull-up exists on all digital IO
LVDS Output
40
Output Offset Voltage
Delta Offset Voltage
Pk to Pk Output Swing
Output Transition Time
4
Rise Time
Fall Time
Frequency
Output Duty Cycle
Period Jitter
5
Integrated Phase Noise
tR
tF
CLK1
SYM
JPER
JPH
R = 100Ohms Differential
1.125
1.4
50
V
mV
mV
Single-Ended
20% to 80%
RL = 100Ohms, CL = 2pF
[FS1, FS0] = [1, 1]
Differential
F0 = 156.25MHz
200kHz to 20MHz @ 156.25MHz
100kHz to 20MHz @ 156.25MHz
12kHz to 20MHz @ 156.25MHz
48
350
200
100
52
2.5
0.28
0.4
1.7
350
ps
MHz
%
psRMS
2
psRMS
Notes:
1. Pin 12 VDD2, and pin 13 VDD should be filtered with 0.1uF capacitors.
2. Output is enabled if OE pin is floated or not connected.
3. tSU is time to 100ppm stable output frequency after VDD is applied and outputs are enabled.
4. Output Waveform and Test Circuit figures below define the parameters.
5. Period Jitter includes crosstalk from adjacent output.
February 28, 2017
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Microchip Technology Inc.
DSC2030FE5-B0018
Nominal Performance Parameters
(Unless specified otherwise: T = 25°C, VDD = 3.3V)
Figure 1. LVDS Phase Jitter (integrated phase noise)
LVDS Output Waveform
350
OE
Figure 2. LVDS Output Waveform
MSL 1 @ 260°C refer to JSTD-020C
Ramp-Up Rate (200°C to Peak Temp)
Preheat Time 150°C to 200°C
Time maintained above 217°C
Peak Temperature
Time within 5°C of actual Peak
Ramp-Down Rate
Time 25°C to Peak Temperature
3°C/sec Max.
60 - 180 sec
60 - 150 sec
255 - 260°C
20 - 40 sec
6°C/sec Max.
8 min Max.
February 28, 2017
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Embedded System
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