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70V27S55PFI

Description
IC SRAM 512K PARALLEL 100TQFP
Categorystorage   
File Size209KB,21 Pages
ManufacturerIDT (Integrated Device Technology, Inc.)
Websitehttp://www.idt.com/
Download Datasheet Parametric View All

70V27S55PFI Overview

IC SRAM 512K PARALLEL 100TQFP

70V27S55PFI Parametric

Parameter NameAttribute value
memory typeVolatile
memory formatSRAM
technologySRAM - dual port, asynchronous
storage512Kb (32K x 16)
Write cycle time - words, pages55ns
interview time55ns
memory interfacein parallel
Voltage - Power3 V ~ 3.6 V
Operating temperature-40°C ~ 85°C(TA)
Installation typesurface mount
Package/casing100-LQFP
Supplier device packaging100-TQFP(14x14)
HIGH-SPEED 3.3V
32K x 16 DUAL-PORT
STATIC RAM
IDT70V27S/L
LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018
Features:
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
High-speed access
– Commercial: 15/20/25/35/55ns (max.)
– Industrial: 15/20/35ns (max.)
Low-power operation
– IDT70V27S
Active: 500mW (typ.)
Standby: 3.3mW (typ.)
– IDT70V27L
Active: 500mW (typ.)
Standby: 660
μ
W (typ.)
Separate upper-byte and lower-byte control for bus
matching capability
On-chip port arbitration logic
Dual chip enables allow for depth expansion without
external logic
IDT70V27 easily expands data bus width to 32 bits or more
using the Master/Slave select when cascading more than
one device
M/S = V
IH
for
BUSY
output flag on Master,
M/S = V
IL
for
BUSY
input on Slave
Busy and Interrupt Flags
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
LVTTL-compatible, single 3.3V (±0.3V) power supply
Available in 100-pin Thin Quad Flatpack (TQFP)
Industrial temperature range (-40°C to +85°C) is available
for selected speeds
Green parts available, see ordering information
Functional Block Diagram
R/
W
L
UB
L
CE
0L
R/W
R
UB
R
CE
0R
CE
1L
OE
L
LB
L
CE
1R
OE
R
LB
R
I/O
8-15L
I/O
0-7L
BUSY
L
(1,2)
I/O
Control
I/O
Control
I/O
8-15R
I/O
0-7R
BUSY
R
(1,2)
,
A
14L
A
0L
Address
Decoder
A
14L
A
0L
CE
0L
32Kx16
MEMORY
ARRAY
70V27
Address
Decoder
A
14R
A
0R
CE
1L
OE
L
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
A
14R
A
0R
CE
0R
CE
1R
OE
R
R/
W
L
SEM
L
INT
L
(2)
(2)
R/
W
R
SEM
R
(2)
INT
R
3603 drw 01
M/
S
NOTES:
1)
BUSY
is an input as a Slave (M/S=V
IL
) and an output as a Master (M/S=V
IH
).
2)
BUSY
and
INT
are non-tri-state totem-pole outputs (push-pull).
JULY 2018
DSC 3603/16
6.01
1
©
2018
Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.

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