Digital Multi-Phase Buck Controller
IR3536/38
CHL8326/28
FEATURES
6-phase & 8-phase dual output PWM Controller
Phases are flexibly assigned between Loops 1 & 2
Intel® VR12, AMD® 3.4MHz SVI/PVI & Memory
modes
Overclocking & Gaming Mode with Vmax setting
Switching frequency from 200kHz to 1.2MHz per
phase
IR Efficiency Shaping Features including Variable
Gate Drive and Dynamic Phase Control
Programmable 1-phase or 2-phase for Light Loads
and Active Diode Emulation for Very Light Loads
IR Adaptive Transient Algorithm (ATA) on both loops
minimizes output bulk capacitors and system cost
Auto-Phase Detection with auto-compensation
Per-Loop Fault Protection: OVP, UVP, OCP, OTP, CFP
I2C/SMBus/PMBus system interface for telemetry
of Temperature, Voltage, Current & Power for
both loops
Non-Volatile Memory (NVM) for custom
configuration
Compatible with IR ATL and 3.3V Tri-state Drivers
+3.3V supply voltage; -20ºC to 85ºC ambient
operation
Pb-Free, RoHS, 7x7 48-pin & 8x8 56-pin QFN, MSL2
package
DESCRIPTION
The IR3536/CHL8326 and IR3538/CHL8328 are dual-loop
digital multi-phase buck controllers. The IR3536/CHL8326
drive up to 6 phases and the IR3538/CHL8328 drives up to
8 phases. The IR3536/CHL8326 and IR3538/CHL8328 are
fully Intel® VR12 and AMD® SVI/PVI compliant on both
loops and provide a Vtt tracking function for DDR memory.
The IR3536/CHL8326 and IR3538/CHL8328 include the
IR Efficiency Shaping Technology to deliver exceptional
efficiency at minimum cost across the entire load range.
IR Variable Gate Drive optimizes the MOSFET gate drive
voltage based on real-time load current. IR Dynamic Phase
Control adds/drops phases based upon load current.
The IR3536/CHL8326 and IR3538/CHL8328 can be
configured to enter 1-phase operation and active diode
emulation mode automatically or by command.
IR’s unique Adaptive Transient Algorithm (ATA), based on
proprietary non-linear digital PWM algorithms, minimizes
output bulk capacitors.
The I2C/PMBus interface can communicate with up to 16
IR3536/CHL8326 and IR3538/CHL8328 based VR loops.
Device configuration and fault parameters are easily
defined using the IR Intuitive Power Designer (DPDC) GUI
and stored in on-chip NVM.
The IR3536/CHL8326 and IR3538/CHL8328 provides
extensive OVP, UVP, OCP and OTP fault protection and
includes thermistor based temperature sensing with
VR_HOT signal.
NVM storage saves pins and enables a small package size.
The IR3536/CHL8326 and IR3538/CHL8328 also include
numerous features like register diagnostics for fast design
cycles and platform differentiation, truly simplifying
VRD design and enabling fastest time-to-market with its
“set-and-forget” methodology.
APPLICATIONS
Intel ® VR12 & AMD® SVI & PVI based systems
DDR Memory with Vtt tracking
Overclocked & Gaming platforms
PIN DIAGRAM
ISEN1
ISEN2
ISEN3
ISEN4
ISEN5
IRTN8
ISEN6
44
IRTN1
IRTN2
IRTN3
IRTN4
IRTN5
IRTN6
ISEN1
ISEN2
ISEN3
ISEN4
ISEN5
ISEN6
IRTN1
IRTN2
IRTN3
IRTN4
IRTN5
IRTN6
56
ISEN8
1
2
3
4
5
6
7
8
9
10
11
12
13
55
54
53
52
51
50
49
48
47
46
45
43
42
41
40
39
38
37
ISEN7
RCSP_L2
RCSM_L2
VCC
VSEN_L2
VRTN_L2
PWM8
PWM7
PWM6
PWM5
PWM4
PWM3
PWM2
PWM1
48
RCSP
RCSM
VCC
CFP /
VFIXEN_PSI
2
VSEN
VRTN
RRES
TSEN
V18A
VR_READY
1
/
PWRGD
2
VR_READY_L2
1
/ PWROK
2
VINSEN
1
47
46
45
44
43
42
41
40
39
38
37
36
RCSP_L2
35
RCSM_L2
34
VCC
33
VSEN_L2
32
VRTN_L2
1
2
3
4
5
6
7
8
9
10
11
49
GND
12
13
14
15
16
17
2
RCSP
RCSM
VCC
CFP /
VFIXEN_PSI
2
VSEN
VRTN
RRES
TSEN
V18A
1
CHL8326
48 Pin 7x7 QFN
Top View
31
PWM6
30
PWM5
29
PWM4
28
PWM3
27
PWM2
26
PWM1
CHL8328
56 Pin 8x8 QFN
Top View
IRTN7
36
35
34
33
32
31
30
29
28
VR_READY
1
/
PWRGD
2
VR_READY_L2
1
/ PWROK
2
GPO_B
25
VAR_GATE
VINSEN
57
GND
14
15
16
17
18
19
20
21
22
23
24
25
26
27
18
19
20
21
22
23
24
VR_HOT#
1
/
VRHOT_ICRIT#
2
PSI
1
/ VID[5]
2
SMB_DIO
SV_CLK
1
/ SVC_VID[3]
2
SV_DIO / SVD_VID[2]
PM_ADDR_GPO_C
1
/
PM_ADDR_VID[0]
2
GPO_A
1
/ CBOUT
2
SV_ALERT
1
/ VID[4]
2
SV_ADDR_GPO_D
1
/ VID[1]
2
SMB_ALERT#
SMB_CLK
ENABLE
VR_HOT# /
VRHOT_ICRIT#
2
SMB_DIO
TSEN2
PSI(MPoL)
1
/ VID[5]
2
SV_CLK
1
/ SVC_VID[3]
2
SV_DIO
1
/ SVD_VID[2]
2
1
2
Intel/MPoL mode
AMD mode
Figure 1: IR3536/CHL8326 Package Top View
1
June 21, 2013 | FINAL | V1.09
Figure 2: IR3538/CHL8328 Package Top View
PM_ADDR_GPO_C
1
/
PM_ADDR_VID[0]
2
GPO_A
1
/ CBOUT
2
SV_ALERT
1
/ VID[4]
2
SV_ADDR_GPO_D
1
/ VID[1]
2
1
SMB_ALERT#
VAR_GATE
SMB_CLK
ENABLE
1
京公网安备 11010802033920号
EEWORLD
