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SI3056DC-EVB

Description
DAUGHTERCARD DAA SI3056/SI3018
CategoryDevelopment board/suite/development tools   
File Size3MB,128 Pages
ManufacturerSilicon Laboratories Inc
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SI3056DC-EVB Overview

DAUGHTERCARD DAA SI3056/SI3018

SI3056DC-EVB Parametric

Parameter NameAttribute value
typetelecommunications
FunctionData Acquisition Arrangement (DAA)
Embedded-
IC/parts usedSi3056
Main attributes-
What's includedplate
Auxiliary properties-
S i 3 0 5 0 + S i 3 0 11 / 1 8 / 1 9
P
R O G R A M M A B L E
V
O I C E
D A A S
O L U T I O N S
Features
PCM highway data interface
µ-law/A-law companding
SPI control interface
GCI interface
80 dB dynamic range TX/RX
Line voltage monitor
Loop current monitor
+6 dBm or +3.2 dBm TX/RX level
mode
Parallel handset detection
3 µA on-hook line monitor current
Overload detection
Programmable line interface

AC termination

DC termination

Ring detect threshold

Ringer impedance
TIP/RING polarity detection
Integrated codec and 2- to 4-wire
analog hybrid
Programmable digital hybrid for
near-end echo reduction
Polarity reversal detection
Programmable digital gain in 0.1 dB
increments
Integrated ring detector
Type I and II caller ID support
Pulse dialing support
3.3 V power supply
Daisy-chaining for up to 16 devices
Greater than 5000 V isolation
Patented isolation technology
Ground start and loop start support
Available in Pb-free RoHS-compliant
packages
Ordering Information
See page 106.
Applications
DSL IADs
VoIP gateways
PBX and IP-PBX systems
Voice mail systems
DECT base stations
Package Options
SDITHR
20
Si3050
SDO
SDI
NC
24
23
22
21
NC
The Si3050+Si3011/18/19 Voice DAA chipset provides a highly-programmable
and globally-compliant foreign exchange office (FXO) analog interface. The
solution implements Silicon Laboratories' patented isolation capacitor technology,
which eliminates the need for costly isolation transformers, relays, or
opto-isolators, while providing superior surge immunity for robust field
performance. The Voice DAA is available as a chipset, a system-side device
(Si3050) paired with a line-side device (Si3011/18/19). The Si3050 is available in
a 20-pin TSSOP or a 24-pin QFN. The Si3011/18/19 is available in a 16-pin
TSSOP, a 16-pin SOIC, or a 20-pin QFN and requires minimal external
components. The Si3050 interfaces directly to standard telephony PCM
interfaces.
19
Description
CS
FSYNC
PCKLK
DTX
DRX
RGDT
1
2
3
4
5
6
SCLK
18
17
GND
VDD
VA
C1A
C2A
RESET
Si3050
Top View
GND
16
15
14
13
10
11
TGD
AOUT/INT
RG
NC
NC
DCT2
IGND
17
10
VREG2
DCT
Functional Block Diagram
Si3050
CS
SCLK
SDI
SDO
SDI THRU
PCLK
DTX
DRX
FSYNC
RGDT
RG
TGD
TGDE
RESET
AOUT/INT
Si3011/18/19
QE
NC
16
15 DCT3
14 QB
13 QE2
12 SC
7
RNG1
8
IGND
9
RNG2
11 NC
Si3018/19
RX
NC
RX
IB
C1B
C2B
1
2
3
4
5
6
VREG
20
19
18
Control
Data
Interface
Hybrid, AC
and DC
Terminations
Isolation
Interface
Isolation
Interface
Line
Data
Interface
IB
SC
DCT
VREG
VREG2
DCT2
DCT3
RNG1
RNG2
QB
QE
QE2
IGND
PAD
Ring Detect
Off-Hook
Control
Logic
US Patent# 5,870,046
US Patent# 6,061,009
Rev. 1.5 10/11
Copyright © 2011 by Silicon Laboratories
Si3050 + Si3011/18/19
TGDE
12
7
8
9
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