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MT47H64M16B7-37E:A TR

Description
IC DRAM 1G PARALLEL 92FBGA
Categorystorage   
File Size8MB,137 Pages
ManufacturerMicron Technology
Websitehttp://www.mdtic.com.tw/
Environmental Compliance
Download Datasheet Parametric View All

MT47H64M16B7-37E:A TR Overview

IC DRAM 1G PARALLEL 92FBGA

MT47H64M16B7-37E:A TR Parametric

Parameter NameAttribute value
memory typeVolatile
memory formatDRAM
technologySDRAM - DDR2
storage1Gb (64M x 16)
Clock frequency267MHz
Write cycle time - words, pages15ns
interview time400ps
memory interfacein parallel
Voltage - Power1.7 V ~ 1.9 V
Operating temperature0°C ~ 85°C(TC)
Installation typesurface mount
Package/casing92-VFBGA
Supplier device packaging92-FBGA(11x19)
1Gb: x4, x8, x16 DDR2 SDRAM
Features
DDR2 SDRAM
MT47H256M4 – 32 Meg x 4 x 8 banks
MT47H128M8 – 16 Meg x 8 x 8 banks
MT47H64M16 – 8 Meg x 16 x 8 banks
For the latest data sheet, refer to Micron’s Web site:
http://www.micron.com/ddr2
Features
RoHS compliant
V
DD
= +1.8V ±0.1V, V
DD
Q = +1.8V ±0.1V
JEDEC standard 1.8V I/O (SSTL_18-compatible)
Differential data strobe (DQS, DQS#) option
4-bit prefetch architecture
Duplicate output strobe (RDQS) option for x8
DLL to align DQ and DQS transitions with CK
8 internal banks for concurrent operation
Programmable CAS latency (CL)
Posted CAS additive latency (AL)
WRITE latency = READ latency – 1
t
CK
Programmable burst lengths: 4 or 8
Adjustable data-output drive strength
64ms, 8,192-cycle refresh
On-die termination (ODT)
Industrial temperature (IT) option
Supports JEDEC clock jitter specification
Options
• Configuration
256 Meg x 4 (32 Meg x 4 x 8 banks )
128 Meg x 8 (16 Meg x 8 x 8 banks)
64 Meg x 16 (8 Meg x 16 x 8 banks)
• FBGA package (lead-free)
92-ball FBGA (11mm x 19mm) (:A)
84-ball FBGA (10mm x 16.5mm) (:D)
68-ball FBGA (10mm x 16.5mm) (:D)
• Timing – cycle time
5.0ns @ CL = 3 (DDR2-400)
3.75ns @ CL = 4 (DDR2-533)
3.0ns @ CL = 5 (DDR2-667)
3.0ns @ CL = 4 (DDR2-667)
2.5ns @ CL = 6 (DDR2-800)
2.5ns @ CL = 5 (DDR2-800)
• Self refresh
Standard
Low-power
• Operating temperature
Commercial (0°C
T
C
85°C)
Industrial (–40°C
T
C
95°C; –40°C
T
A
85°C)
• Revision
Marking
256M4
128M8
64M16
BT
B7
B7
-5E
-37E
-3
-3E
-25
-25E
None
L
None
IT
:A/:D
Table 1:
Architecture
Configuration Addressing
256 Meg x 4 128 Meg x 8 64 Meg x 16
8 Meg x 16
x 8 banks
8K
8K (A0–A12)
8 (BA0–BA2)
1K (A0–A9)
Table 2:
Key Timing Parameters
RC
(ns)
55
55
55
54
55
55
t
32 Meg x 4
16 Meg x 4
x 8 banks
x 8 banks
8K
8K
Refresh Count
16K (A0–A13) 16K (A0–A13)
Row Addr.
8 (BA0–BA2) 8 (BA0–BA2)
Bank Addr.
Column Addr. 2K (A0–A9, A11) 1K (A0–A9)
Configuration
Data Rate (MHz)
t
Speed
RCD
t
RP
Grade CL = 3 CL = 4 CL = 5 CL = 6 (ns) (ns)
-5E
-37E
-3
-3E
-25
-25E
400
400
400
N/A
N/A
N/A
400
533
533
667
N/A
533
N/A
N/A
667
667
667
800
N/A
N/A
N/A
N/A
800
N/A
15
15
15
12
15
12.5
15
15
15
12
15
12.5
Note: CL = CAS latency.
PDF: 09005aef821ae8bf/Source: 09005aef821aed36
1GbbDDR2_1.fm - Rev. K 4/06 EN
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
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