ATA663201/ATA663203/ATA663231/ATA663254
LIN Bus Device Family including Voltage Regulator and
LIN SBC
(1)
with Compatible Footprint
DATASHEET
Features
●
Supply voltage up to 40V
●
Operating voltage V
S
= 5V to 28V
●
Supply current
●
Sleep mode: typically 9µA
●
Silent mode: typically 47µA
●
Very low current consumption at low supply voltages (2V < V
S
< 5.5V):
typically 130µA
●
Linear low-drop voltage regulator, 85mA current capability:
●
MLC (multi-layer ceramic) capacitor with 0 ESR
●
Normal, fail-safe, and silent mode
●
Atmel
®
ATA663254: V
CC
= 5.0V ±2%
●
Atmel ATA663231: V
CC
= 3.3V ±2%
●
Sleep mode: VCC is switched off
●
Active mode
●
Atmel ATA663203: V
CC
= 5.0V ±2%
●
Atmel ATA663201: V
CC
= 3.3V ±2%
●
VCC undervoltage detection with open drain reset output (NRES, 4ms reset time)
●
Voltage regulator is short-circuit and over-temperature protected
●
LIN physical layer according to LIN 2.0, 2.1, 2.2, 2.2A and SAEJ2602-2
●
Wake-up capability via LIN bus (100µs dominant)
●
Wake-up source recognition
●
TXD time-out timer
●
Bus pin is over-temperature and short-circuit protected versus GND and battery
●
Advanced EMC and ESD performance
●
Fulfills the OEM “Hardware Requirements for LIN in Automotive Applications
Rev.1.3”
●
Interference and damage protection according to ISO7637
●
Qualified according to AEC-Q100
●
Packages:
●
DFN8 (all types) with wettable flanks (Moisture Sensitivity Level 1)
●
SO8 (only Atmel ATA663254)
Note:
1. LIN SBC: LIN system basis chip including LIN transceiver and voltage
regulator.
9337G-AUTO-09/16
1.
Description
The Atmel
®
ATA6632xx device family includes two basic products; a LIN system basis chip (SBC) and a low-drop voltage
regulator with compatible footprints.
The Atmel ATA663231/54 (system basis chip) is a fully integrated LIN transceiver, designed according to the LIN
specification 2.0, 2.1, 2.2, 2.2A and SAEJ2602-2, with a low-drop voltage regulator (3.3V/5V/85mA). The combination of
voltage regulator and bus transceiver makes it possible to develop simple but powerful slave nodes in LIN bus systems.
Atmel ATA663231/54 is designed to handle the low-speed data communication in vehicles (for example, in convenience
electronics). Improved slope control at the LIN driver ensures secure data communication up to 20Kbaud. The bus output is
designed to withstand high voltage. Sleep mode and silent mode guarantee minimized current consumption even in the case
of a floating or a short-circuited LIN bus.
The Atmel ATA663201/03 (voltage regulator) is a fully integrated low-drop voltage regulator, with 3.3V/5V output voltage and
85mA current capability. It is especially designed for the automotive environment. A key feature is that the current
consumption is always below 170µA (without load), even if the supply voltage is below the regulator’s nominal output
voltage.
Table 1-1.
Description
LIN-SBC with 3.3V regulator
LIN-SBC with 5V regulator
Voltage regulator 3.3V
Voltage regulator 5V
ATA6632xx Device Family
Atmel ATA6632xx
31
54
01
03
Figure 1-1. Block Diagram LIN Transceiver with Integrated Voltage Regulator (SBC)
Atmel ATA663231/54
V
CC
Receiver
RXD
1
7
VS
-
+
Normal and
Fail-safe
Mode
6
RF-filter
LIN
V
CC
Wake-up bus timer
Short-circuit and
overtemperature
protection
TXD
4
TXD
Time-out
timer
Slew rate control
8
EN
2
Sleep
mode
Control
VCC
unit
switched
off
Voltage regulator
Normal/Silent/
Fail-safe Mode
3.3V/5V
Undervoltage reset
V
CC
3
VCC
NRES
GND
5
2
ATA663201/ATA663203/ATA663231/ATA663254 [DATASHEET]
9337G–AUTO–09/16
Figure 1-2. Block Diagram Voltage Regulator
VS
7
Voltage
Reference
PMOS
+
-
8
VCC
3
Undervoltage
Reset
NRES
Atmel ATA663201/03
5
GND
ATA663201/ATA663203/ATA663231/ATA663254 [DATASHEET]
9337G–AUTO–09/16
3
2.
Pin Configuration
Figure 2-1. Pinning DFN8
RXD
EN
NRES
TXD
ATA663231
ATA663254
DFN8
3x3
VCC
VS
LIN
GND
NC
NC
NRES
NC
ATA663201
ATA663203
DFN8
3x3
VCC
VS
NC
GND
SBC
Voltage regulator
Figure 2-2. Pinning SO8
ATA663254
RXD
EN
NRES
TXD
1
8
2
7
SO8
3
6
4
5
VCC
VS
LIN
GND
Table 2-1.
Pin
1
2
3
4
5
6
7
8
Pin Description
Symbol
RXD
EN
NRES
TXD
GND
LIN
VS
VCC
Function
Receive data output
Enables normal mode if the input is high
VCC undervoltage output, open drain, low at reset
Transmit data input
Ground
LIN bus line input/output
Supply voltage
Output voltage regulator 3.3V/5V/85mA
Backside
(1)
Heat slug, internally connected to the GND pin
Note:
1. Only for the DFN8 package.
4
ATA663201/ATA663203/ATA663231/ATA663254 [DATASHEET]
9337G–AUTO–09/16
3.
3.1
Pin Description
Supply Pin (VS)
LIN operating voltage is V
S
= 5V to 28V. Undervoltage detection is implemented to disable transmission if V
S
falls below typ.
4.5V, thereby avoiding false bus messages. After switching on V
S
, the IC starts in fail-safe mode and the voltage regulator is
switched on.
The supply current in sleep mode is typically 9µA and 47µA in silent mode.
3.2
Ground Pin (GND)
The IC does not affect the LIN bus in the event of GND disconnection. It is able to handle a ground shift of up to 11.5% of V
S
.
3.3
Voltage Regulator Output Pin (VCC)
The internal 3.3V/5V voltage regulator is capable of driving loads up to 85mA, supplying the microcontroller and other ICs on
the PCB and is protected against overload by means of current limitation and overtemperature shutdown. Furthermore, the
output voltage is monitored and causes a reset signal at the NRES output pin if it drops below a defined threshold
V
VCC_th_uv_down
.
3.4
Undervoltage Reset Output (NRES)
If the V
CC
voltage falls below the undervoltage detection threshold V
CC_th_uv_down
, NRES switches to low after t
res_f
. The
NRES stays low even if V
CC
= 0V because NRES is internally driven from the V
S
voltage. If V
S
voltage ramps down, NRES
stays low until V
S
< 1.5V and then becomes highly impedant.
The implemented undervoltage delay keeps NRES low for t
Reset
= 4ms after V
CC
reaches its nominal value.
3.5
Bus Pin (LIN) (SBC only)
A low-side driver with internal current limitation and thermal shutdown as well as an internal pull-up resistor according to LIN
specification 2.x is implemented. The voltage range is from –27V to +40V. This pin exhibits no reverse current from the LIN
bus to V
S
, even in the event of a GND shift or V
Bat
disconnection. The LIN receiver thresholds comply with the LIN protocol
specification.
The fall time (from recessive to dominant) and the rise time (from dominant to recessive) are slope-controlled.
During a short circuit at LIN to V
Bat
, the output limits the output current to I
BUS_LIM
. Due to the power dissipation, the chip
temperature exceeds T
LINoff
and the LIN output is switched off. The chip cools down and after a hysteresis of T
hys
, switches
the output on again. RXD stays on high because LIN is high. The V
CC
regulator works independently during LIN
overtemperature switch-off.
During a short circuit from LIN to GND the IC can be switched into sleep or silent mode and even in this case the current
consumption is lower than 100µA in sleep mode and lower than 120µA in silent mode. If the short-circuit disappears, the IC
starts with a remote wake-up.
The reverse current is < 2µA at pin LIN during loss of V
Bat
. This is optimal behavior for bus systems where some slave nodes
are supplied from battery or ignition.
ATA663201/ATA663203/ATA663231/ATA663254 [DATASHEET]
9337G–AUTO–09/16
5
Analogue and Mixed Signal
京公网安备 11010802033920号
EEWORLD
