eGaN® FET DATASHEET
EPC8009
EPC8009 – Enhancement Mode Power Transistor
V
DS
, 65 V
R
DS(on)
, 130 mΩ
I
D
, 4 A
D
G
EFFICIENT POWER CONVERSION
S
HAL
Gallium Nitride is grown on Silicon Wafers and processed using standard CMOS equipment
leveraging the infrastructure that has been developed over the last 55 years. GaN’s exceptionally
high electron mobility and low temperature coefficient allows very low R
DS(on)
, while its lateral device
structure and majority carrier diode provide exceptionally low Q
G
and zero Q
RR
. The end result is a
device that can handle tasks where very high switching frequency, and low on-time are beneficial as
well as those where on-state losses dominate.
EPC8009 eGaN FETs are supplied only in
passivated die form with solder bars
Die Size: 2.1 mm x 0.85 mm
Applications
• Ultra High Speed DC-DC Conversion
• RF Envelope Tracking
• Wireless Power Transfer
• Game Console and Industrial Movement
Sensing (LiDAR)
Benefits
• Ultra High Efficiency
• Ultra Low R
DS(on)
• Ultra Low Q
G
• Ultra Small Footprint
www.epc-co.com/epc/Products/eGaNFETs/EPC8009.aspx
Maximum Ratings
PARAMETER
V
DS
I
D
V
GS
T
J
T
STG
Drain-to-Source Voltage (Continuous)
Drain-to-Source Voltage (up to 10,000 5 ms pulses at 125°C)
Continuous (T
A
= 25˚C, R
θJA
= 33°C/W)
Pulsed (25°C, T
PULSE
= 300 µs)
Gate-to-Source Voltage
Gate-to-Source Voltage
Operating Temperature
Storage Temperature
VALUE
65
78
4
7.5
6
–4
–40 to 150
–40 to 150
UNIT
V
A
V
°C
PARAMETER
BV
DSS
I
DSS
I
GSS
V
GS(TH)
R
DS(on)
V
SD
Drain-to-Source Voltage
Drain-Source Leakage
Static Characteristics (T
J
= 25°C unless otherwise stated)
TEST CONDITIONS
V
GS
= 0 V, I
D
= 125 µA
V
DS
= 52 V, V
GS
= 0 V
V
GS
= 5 V
V
GS
= -4 V
V
DS
= V
GS
, I
D
= 0.25 mA
V
GS
= 5 V, I
D
= 0.5 A
I
S
= 0.5 A, V
GS
= 0 V
MIN
65
TYP
50
100
50
MAX
100
500
100
2.5
130
UNIT
V
µA
µA
V
mΩ
V
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Gate Threshold Voltage
Drain-Source On Resistance
Source-Drain Forward Voltage
0.8
1.4
90
2.2
Specifications are with substrate shorted to source where applicable.
Thermal Characteristics
PARAMETER
R
0JC
R
0JB
R
0JA
Thermal Resistance, Junction-to-Case
Thermal Resistance, Junction-to-Board
Thermal Resistance, Junction-to-Ambient (Note 1)
TYP
8.2
16
82
UNIT
°C/W
Note 1: R
θJA
is determined with the device mounted on one square inch of copper pad, single layer 2 oz copper on FR4 board.
See
http://epc-co.com/epc/documents/product-training/Appnote_Thermal_Performance_of_eGaN_FETs.pdf
for details
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| COPYRIGHT 2018 |
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eGaN® FET DATASHEET
Dynamic Characteristics (T
J
= 25˚C unless otherwise stated)
PARAMETER
C
ISS
C
OSS
C
RSS
R
G
Q
G
Q
GS
Q
GD
Q
G(TH)
Q
OSS
Q
RR
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Gate Resistance
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain Charge
Gate Charge at Threshold
Output Charge
Source-Drain Recovery Charge
V
GS
= 0 V, V
DS
= 32.5 V
V
DS
= 32.5 V, V
GS
= 5 V, I
D
= 1 A
V
GS
= 0 V, V
DS
= 32.5 V
EPC8009
TEST CONDITIONS
MIN
TYP
45
19
0.5
0.3
370
120
55
96
940
0
MAX
52
28
0.8
UNIT
pF
Ω
450
94
1400
pC
Specifications are with substrate shorted to source where applicable.
Figure 1: Typical Output Characteristics at 25°C
8
7
6
V
GS
= 5
V
GS
= 4
V
GS
= 3
V
GS
= 2
8
7
6
Figure 2: Transfer Characteristics
25˚C
125˚C
V
DS
= 3 V
I
D
– Drain Current (A)
5
4
3
2
1
0
0
0.5
1
1.5
2
2.5
3
I
D
– Drain Current (A)
5
4
3
2
1
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
V
DS
– Drain-to-Source Voltage (V)
V
GS
– Gate-to-Source Voltage (V)
400
Figure 3: R
DS(on)
vs. V
GS
for Various Drain Currents
R
DS(on)
– Drain-to-Source Resistance (m )
I
D
= 0.5 A
I
D
= 1.0 A
I
D
= 1.5 A
I
D
= 2.0 A
400
350
300
250
200
150
100
50
Figure 4: R
DS(on)
vs. V
GS
for Various Temperatures
25˚C
125˚C
I
D
= 1 A
R
DS(on)
– Drain-to-Source Resistance (m )
350
300
250
200
150
100
50
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
2
2.5
3
3.5
4
4.5
5
V
GS
– Gate-to-Source Voltage (V)
V
GS
– Gate-to-Source Voltage (V)
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| COPYRIGHT 2018 |
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eGaN® FET DATASHEET
Figure 5: Capacitance (Linear Scale)
10
50
40
2
EPC8009
Figure 5A: Capacitance (Log Scale)
C – Capacitance (pF)
30
20
10
0
C
OSS
= C
GD
+ C
SD
C
ISS
= C
GD
+ C
GS
C
RSS
= C
GD
C – Capacitance (pF)
10
1
C
OSS
= C
GD
+ C
SD
C
ISS
= C
GD
+ C
GS
C
RSS
= C
GD
10
0
0
10
20
30
40
50
60
10
-1
0
10
20
30
40
50
60
V
DS
– Drain-to-Source Voltage (V)
V
DS
– Drain-to-Source Voltage (V)
Figure 6: Gate Charge
5
I
D
= 1 A
V
DS
= 32.5 V
8
7
Figure 7: Reverse Drain-Source Characteristics
25˚C
125˚C
I
SD
– Source-to-Drain Current (A)
100
200
300
400
4
6
5
4
3
2
1
V
G
– Gate Voltage (V)
3
2
1
0
0
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
Q
G
– Gate Charge (pC)
V
SD
– Source-to-Drain Voltage (V)
Figure 8: Normalized R
DS(on)
1.8
Figure 9: Normalized Threshold Voltage vs. Temperature
1.3
I
D
= 0.25 mA
Normalized On-State Resistance - R
DS(on)
1.6
Normalized Threshold Voltage (V)
25
50
75
100
125
150
I
D
= 1 A
V
GS
= 5 V
1.2
1.1
1.0
0.9
0.8
0.7
1.4
1.2
1
0.8
0
0.6
0
25
50
75
100
125
150
T
J
– Junction Temperature (°C)
T
J
– Junction Temperature (°C)
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| COPYRIGHT 2018 |
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eGaN® FET DATASHEET
Figure 10: Gate Current
1.4
1.2
25˚C
125˚C
EPC8009
Figure 11: Smith Chart
S-Parameter Characteristics
V
GSQ
= 2.36 V, V
DSQ
= 30 V, I
DQ
= 0.50 A
Pulsed Measurement, Heat-Sink Installed, Z
0
= 50 Ω
0.9
I
G
– Gate Current (mA)
1.0
1
0.8
0.7
0 .6
1.2
1.4
1.6
1.8
0.8
0.6
0.1
S11 – Gate Re ection
S22 – Drain Re ection
EPC8009
0.
2 .0
5
0.
4
3.
4.0
5.0
0
0.4
0.2
0
0
1
2
3
4
5
6
0.2
0.9
1.2
0.5
0.6
0.7
0.8
1.4
1.8
3.0
4.0
0.1
0.3
0.4
1.0
1.6
2.0
5.0
10
0
0.3
0.
4
0.7
0.8
0.9
All measurements were done with substrate shortened to source.
Figure 12: Gain Chart
Amplitude
[dB]
45
40
35
30
25
20
15
10
5
0
100
1000
Gmax
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
–0.2
Figure 13: Device Reflection
1.0
1.2
1.4
1.6
V
GS
– Gate-to-Source Voltage (V)
200
MHz
200
MHz
1.8
2 .0
0.
5
0 .6
Z
DS
Z
GS
Frequency (MHz)
Figure 14: Taper and Reference Plane details – Device Connection
Micro-Strip design: 2-layer
½ oz (17.5 µm) thick copper
30 mil thick RO4350 substrate
Frequency
[MHz]
200
500
1000
1200
1500
2000
2400
3000
Gate (Z
GS
)
[Ω]
1.98 – j8.58
1.87 – j2.15
1.39 + j2.14
1.21 + j3.56
1.01 + j4.96
0.83 + j7.83
0.73 + j10.14
0.58 + j14.27
Drain (Z
DS
)
[Ω]
16.83 – j11.29
5.22 – j5.45
3.53 – j3.42
2.35 – j0.81
1.54 + j6.19
1.84 + j10.20
Device Outline
Gate Circuit
Reference Plane
1000
1621
914
355
914
10.69 – j9.69
271
271
3.
0
All dimensions in µm
1.57 + j3.52
S-Parameter Table - Download S-parameter files at
www.epc-co.com
149
Drain Circuit
Reference Plane
EPC – EFFICIENT POWER CONVERSION CORPORATION |
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| COPYRIGHT 2018 |
1621
4.0
RF Café
2002
5.0
0.2
8.0
10
0.1
20
6.0
0.3
0.2
3
GHz
GHz
6.0
8.0
10
20
| 4
eGaN® FET DATASHEET
EPC8009
Figure 15:
Transient Thermal Response Curves
Junction-to-Board
Z
θJB
Normalized Thermal Impedance
1
Duty Factors:
0.5
0.2
0.1
0.05
P
DM
t
p
T
0.1
0.02
0.01
0.01
Single Pulse
0.001
10
-5
Notes:
Duty Factor = t
p
/T
Peak T
J
= P
DM
x Z
θJB
x R
θJB
+ T
B
10
-3
10
-4
t
p
– Rectangular Pulse Duration (s)
Junction-to-Case
10
-2
10
-1
1
10
100
1
Z
θJC
Normalized Thermal Impedance
Duty Factors:
0.5
0.2
0.1
0.05
0.1
T
P
DM
t
p
0.02
0.01
0.01
Single Pulse
0.001
10
-6
Notes:
Duty Factor = t
p
/T
Peak T
J
= P
DM
x Z
θJC
x R
θJC
+ T
C
10
-4
10
-3
10
-2
10
-1
1
10
10
-5
t
p
– Rectangular Pulse Duration (s)
Figure 16: Safe Operating Area
10
I
D
- Drain Current (A)
1
Pulse Width (s)
100 ms
10 ms
1 ms
100 µs
0.1
0.1
1
10
V
DS
– Drain Voltage (V)
100
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| COPYRIGHT 2018 |
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