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LTC2155IUP-12#TRPBF

Description
IC ADC DUAL 12BIT 170M 64-QFN
CategoryAnalog mixed-signal IC    converter   
File Size914KB,32 Pages
ManufacturerLinear ( ADI )
Websitehttp://www.analog.com/cn/index.html
Environmental Compliance
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LTC2155IUP-12#TRPBF Overview

IC ADC DUAL 12BIT 170M 64-QFN

LTC2155IUP-12#TRPBF Parametric

Parameter NameAttribute value
Brand NameLinear Technology
Is it Rohs certified?conform to
MakerLinear ( ADI )
Parts packaging codeQFN
package instructionHVQCCN, LCC64,.35SQ,20
Contacts64
Manufacturer packaging codeUP
Reach Compliance Codecompliant
ECCN code3A991.C.2
Maximum analog input voltage1.5 V
Minimum analog input voltage-1.5 V
Converter typeADC, PROPRIETARY METHOD
JESD-30 codeS-PQCC-N64
JESD-609 codee3
length9 mm
Maximum linear error (EL)0.0464%
Humidity sensitivity level1
Number of analog input channels2
Number of digits12
Number of functions1
Number of terminals64
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Output bit codeOFFSET BINARY, 2\'S COMPLEMENT BINARY
Output formatPARALLEL, WORD
Package body materialPLASTIC/EPOXY
encapsulated codeHVQCCN
Encapsulate equivalent codeLCC64,.35SQ,20
Package shapeSQUARE
Package formCHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply1.8 V
Certification statusNot Qualified
Sampling rate170 MHz
Sample and hold/Track and holdSAMPLE
Maximum seat height0.8 mm
Nominal supply voltage1.8 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceMatte Tin (Sn)
Terminal formNO LEAD
Terminal pitch0.5 mm
Terminal locationQUAD
Maximum time at peak reflow temperatureNOT SPECIFIED
width9 mm
LTC2157-12/
LTC2156-12/LTC2155-12
Dual 12-Bit 250Msps/
210Msps/170Msps ADCs
FEATURES
n
n
n
n
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n
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n
DESCRIPTION
The
LTC
®
2157-12/LTC2156-12/LTC2155-12
are a family of
dual 250Msps/210Msps/170Msps 12-bit A/D converters
designed for digitizing high frequency, wide dynamic range
signals. They are perfect for demanding communications
applications with AC performance that includes 68.5dB
SNR and 90dB spurious free dynamic range (SFDR). The
1.25GHz input bandwidth allows the ADC to achieve high
undersampling ratio with very low attenuation. The latency
is only six clock cycles.
DC specs include ±0.26LSB INL (typ), ±0.16LSB DNL (typ)
and no missing codes over temperature. The transition
noise is 0.54LSB
RMS
.
The digital outputs are double data rate (DDR) LVDS.
The ENC
+
and ENC
inputs can be driven differentially with
a sine wave, PECL, LVDS, TTL, or CMOS inputs. An optional
clock duty cycle stabilizer allows high performance at full
speed for a wide range of clock duty cycles.
L,
LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
68.5dB SNR
90dB SFDR
Low Power: 628mW/592mW/545mW Total
Single 1.8V Supply
DDR LVDS Outputs
Easy-to-Drive 1.5V
P-P
Input Range
1.25GHz Full-Power Bandwidth S/H
Optional Clock Duty Cycle Stabilizer
Low Power Sleep and Nap Modes
Serial SPI Port for Configuration
Pin Compatible 14-Bit Versions
64-Lead (9mm × 9mm) QFN Package
APPLICATIONS
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Communications
Cellular Basestations
Software Defined Radios
Medical Imaging
High Definition Video
Testing and Measurement Instruments
TYPICAL APPLICATION
V
DD
CHANNEL A
ANALOG
INPUT
12-BIT
PIPELINED
ADC CORE
CORRECTION
LOGIC
OUTPUT
DRIVERS
OV
DD
DA10_11
DA0_1
LTC2157-12: 32K Points 2-Tone FFT,
f
IN
= 71MHZ and 69MHz, 250Msps
DDR
LVDS
0
–20
AMPLITUDE (dBFS)
DDR
LVDS
–40
–60
–80
S/H
CLOCK
CLOCK/DUTY
CYCLE
CONTROL
OGND
CHANNEL B
OV
DD
ANALOG
INPUT
S/H
12-BIT
PIPELINED
ADC CORE
GND
CORRECTION
LOGIC
OUTPUT
DRIVERS
DB10_11
DB0_1
–100
–120
0
20
40
60
80
100
FREQUENCY (MHz)
120
21576512 TA01
OGND
21576512 G11
21576512fb
For more information
www.linear.com/LTC2157-12
1

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