DEMO MANUAL DC1762A
LTC2165, LTC2164, LTC2163
LTC2162, LTC2161, LTC2160, LTC2159, LTC2269
16-Bit, 20Msps to125Msps ADCs
Description
Demonstration circuit 1762A supports a family of 16-Bit
20Msps to 125Msps ADCs. Each assembly features one
of the following devices: LTC
®
2165, LTC2164, LTC2163,
LTC2162, LTC2161, LTC2160, LTC2159, or LTC2269 high
speed, high dynamic range ADCs.
Demonstration circuit 1762A supports the LTC2165 family
DDR LVDS output mode.
The versions of the 1762A demo board supporting the
LTC2165 series of A/D converters are listed in Table 1.
Table 1. DC1762A Variants
DC1762A VARIANTS
1762A-A
1762A-B
1762A-C
1762A-D
1762A-E
1762A-F
1762A-G
1762A-H
ADC PART NUMBER
LTC2165
LTC2164
LTC2163
LTC2162
LTC2161
LTC2160
LTC2159
LTC2269
RESOLUTION
16-Bit
16-Bit
16-Bit
16-Bit
16-Bit
16-Bit
16-Bit
16-Bit
MAXIMUM SAMPLE RATE
125Msps
105Msps
80Msps
65Msps
40Msps
25Msps
20Msps
20Msps
INPUT FREQUENCY
5MHz to 140MHz
5MHz to 140MHz
5MHz to 140MHz
5MHz to 140MHz
5MHz to 140MHz
5MHz to 140MHz
5MHz to 140MHz
5MHz to 140MHz
Depending on the required resolution and sample rate,
the DC1762A is supplied with the appropriate ADC. The
circuitry on the analog inputs is optimized for analog input
frequencies from 5MHz to 140MHz. Refer to the data sheet
for proper input networks for different input frequencies.
Design files for this circuit board are available at
http://www.linear.com/demo
L,
LT, LTC, LTM, µModule, Linear Technology and the Linear logo are registered trademarks
and PScope is a trademark of Linear Technology Corporation. All other trademarks are the
property of their respective owners.
performance summary
PARAMETER
Supply Voltage – DC1762A
Analog Input Range
Logic Input Voltages
Logic Output Voltages (Differential)
(T
A
= 25°C)
MIN
4.5
1
1.3
0.6
350
1.25
247
1.25
0
0.2
3.6
3.6
TYP
MAX
6
2
UNITS
V
V
P-P
V
V
mV
V
mV
V
V
V
CONDITIONS
Depending on Sampling Rate and the A/D Converter
Provided, this Supply Must Provide up to 500mA.
Depending on SENSE Pin Voltage
Minimum Logic High
Maximum Logic Low
Nominal Logic Levels (100Ω Load, 3.5mA Mode)
Common Mode
Minimum Logic Levels (100Ω Load, 3.5mA Mode)
Common Mode
See Table 1
Single-Ended Encode Mode (ENC
–
Tied to GND)
Differential Encode Mode (ENC
–
Not Tied to GND)
See Table 1
See Table 1
See Applicable Data Sheet
See Applicable Data Sheet
Sampling Frequency (Convert Clock Frequency)
Convert Clock Level
Resolution
Input Frequency Range
SFDR
SNR
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DEMO MANUAL DC1762A
Quick start proceDure
Demonstration circuit 1762A is easy to set up to evaluate
the performance of the LTC2165 A/D converter family. Refer
to Figure 1 for proper measurement equipment setup and
follow the procedure below:
Setup
If a DC890 USB demonstration circuit was supplied with
the DC1762A demonstration circuit, follow the DC890
Quick Start Guide to install the required software and for
connecting the DC890 to the DC1762A and to a PC.
DC1762 Demonstration Circuit Board Jumpers
The DC1762A demonstration circuit board should have
the following jumper settings as default positions: (as
per Figure 1)
JP2 PAR/SER: Selects parallel or serial programming
mode. (default: serial)
JP3 Duty Cycle Stabilizer: enables/disables duty cycle
stabilizer. (default: enable)
JP4 SHDN: Enables and disables the LTC2165. (default:
enable)
JP5 NAP: Enables and disables NAP mode. (default:
enable)
JP6 LVDS/CMOS: Selects between LVDS and CMOS
output signaling. (default: LVDS)
4.5V TO 6V
ANALOG INPUT
PARALLEL DATA
OUTPUT TO DC890
PARALLEL/SERIAL
PROGRAMMING MODE
DUTY CYCLE
STABILIZER
SHDN
LVDS/CMOS
SINGLE-ENDED
ENCODE CLOCK
FROM DC1075
NAP
dc1762a F01
Figure 1. DC1762 Setup
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DEMO MANUAL DC1762A
Quick start proceDure
Applying Power and Signals to the DC1762A
Demonstration Circuit
If a DC890 is used to acquire data from the DC1762A,
the DC890 must FIRST be connected to a powered USB
port or provided an external 6V to 9V BEFORE applying
4.5V to 6V across the pins marked V
+
and GND on the
DC1762A. DC1762A requires 4.5V for proper operation.
Regulators on the board produce the voltages required for
the ADC. The DC1762A demonstration circuit requires up
to 500mA depending on the sampling rate and the A/D
converter supplied.
The DC890 data collection board is powered by the USB
cable and does require an external power supply when
collecting data from and LVDS demo board. It must be
supplied an external 6V to 9V on turrets G7(+) and G1(–)
or the adjacent 2.1mm power jack.
Analog Input Network
For optimal distortion and noise performance the RC net-
work on the analog inputs may need to be optimized for
different analog input frequencies. For input frequencies
above 140MHz, refer to the respective ADC data sheet
for a proper input network. Other input networks may be
more appropriate for input frequencies less than 5MHz,
or above 140MHz.
In almost all cases, filters will be required on both analog
input and encode clock to provide data sheet SNR. In the
case of the DC1762A, a bandpass filter used for the clock
should be used prior to the DC1075 clock divider board.
The filters should be located close to the inputs to avoid
reflections from impedance discontinuities at the driven
end of a long transmission line. Most filters do not present
50Ω outside the passband. In some cases, 3dB to 10dB
pads may be required to obtain low distortion.
If your generator cannot deliver full-scale signals without
distortion, you may benefit from a medium power amplifier
based on a Gallium Arsenide Gain block prior to the final
filter. This is particularly true at higher frequencies where
IC based operational amplifiers may be unable to deliver
the combination of low noise figure and High IP3 point
required. A high order filter can be used prior to this final
amplifier, and a relatively lower Q filter used between the
amplifier and the demo circuit.
Apply the analog input signal of interest to the SMA
connector on the DC1762A demonstration circuit board
marked J5 AIN
+
. This input is capacitively coupled to a
Balun transformer ETC1-1-13 (lead free part number:
MABA007159-000000).
Encode Clock
NOTE: Apply an encode clock to the SMA connector on
the DC1762A demonstration circuit board marked J3
ENC
+
. As a default the DC1762A is populated to have a
single-ended input.
For the best noise performance, the encode input must
be driven with a very low jitter, square wave source. The
amplitude should be large, up to 3V
P-P
or 13dBm. When
using a sinusoidal signal generator a squaring circuit can
be used. Linear Technology also provides demo board
DC1075 that divides a high frequency sine wave by four,
producing a low jitter square wave for best results with
the LTC2165.
Using bandpass filters on the clock and the analog input will
improve the noise performance by reducing the wideband
noise power of the signals. In the case of the DC1762A a
bandpass filter used for the clock should be used prior to
the DC1075. Datasheet FFT plots are taken with 10 pole LC
filters made by TTE (Los Angeles, CA) to suppress signal
generator harmonics, non-harmonically related spurs and
broadband noise. Low phase noise Agilent 8644B genera-
tors are used with TTE bandpass filters for both the clock
input and the analog input.
An internally generated conversion clock output is available
on J1 which could be collected via a logic analyzer, or other
data collection system if populated with a SAMTEC MEC8-
150 type connector or collected by the DC890 QuikEval-II
Data Acquisition Board using PScope™ software.
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DEMO MANUAL DC1762A
Quick start proceDure
Software
The DC890 is controlled by the PScope System Software
provided or downloaded from the Linear Technology
website at http://www.linear.com/software/. If a DC890
was provided, follow the DC890 Quick Start Guide and
the instructions below.
To start the data collection software if PScope.exe, is in-
stalled (by default) in \Program Files\LTC\PScope\, double
click the PScope icon or bring up the run window under
the start menu and browse to the PScope directory and
select PScope.
If the DC1762A demonstration circuit is properly connected
to the DC890, PScope should automatically detect the
DC1762A, and configure itself accordingly. If necessary
the procedure below explains how to manually configure
PScope.
Under the Configure menu, go to ADC Configuration…
Check the Config Manually box and use the following
configuration options, see Figure 2.
Manual Configuration settings:
Bits: 16
Alignment: 16
FPGA Ld: DDR LVDS
Channs: 2
Bipolar: Unchecked
Positive-Edge Clk: Unchecked
If everything is hooked up properly, powered and a suit-
able convert clock is present, clicking the Collect button
should result in time and frequency plots displayed in
Figure 2: ADC Configuration
the PScope window. Additional information and help for
PScope is available in the DC890 Quick Start Guide and in
the online help available within the PScope program itself.
Serial Programming
PScope has the ability to program the DC1762A board
serially through the DC890. There are several options
available in the LTC2165 family that are only available
through serially programming. PScope allows all of these
features to be tested.
These options are available by first clicking on the Set
Demo Bd Options icon on the PScope toolbar (Figure 3).
This will bring up the menu shown in Figure 4.
Figure 3: PScope Toolbar
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DEMO MANUAL DC1762A
Quick start proceDure
Clock Inversion:
Selects the polarity of the CLKOUT signal:
• Normal (Default): Normal CLKOUT polarity
• Inverted: CLKOUT polarity is inverted
Clock Delay:
Selects the phase delay of the CLKOUT signal:
• None (Default): No CLKOUT delay
• 45 deg: CLKOUT delayed by 45 degrees
• 90 deg: CLKOUT delayed by 90 degrees
• 135 deg: CLKOUT delayed by 135 degrees
Clock Duty Cycle:
Enables or disables duty cycle stabilizer
• Stabilizer off (Default): Duty cycle stabilizer disabled
• Stabilizer on: Duty cycle stabilizer enabled
Output Current:
Selects the LVDS output drive current
• 1.75mA (Default): LVDS output driver current
• 2.1mA: LVDS output driver current
• 2.5mA: LVDS output driver current
• 3.0mA: LVDS output driver current
• 3.5mA: LVDS output driver current
Figure 4: Demobd Configuration Options
• 4.0mA: LVDS output driver current
• 4.5mA: LVDS output driver current
Internal Termination:
Enables LVDS internal termination
• Off (Default): Disables internal termination
• On: Enables internal termination
Outputs:
Enables digital outputs
• Enabled (Default): Enables digital outputs
• Disabled: Disables digital outputs
This menu allows any of the options available for the
LTC2165 family to be programmed serially. The LTC2165
family has the following options:
Power Down:
Selects between normal operation, nap,
and sleep modes:
• Normal (Default): Entire ADC is powered, and active.
• Nap: ADC core powers down while references stay
active.
• Shutdown: The entire ADC is powered down.
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