FAN5109B — Dual Bootstrapped 12V MOSFET Driver
August 2007
FAN5109B
Dual Bootstrapped 12V MOSFET Driver
Features
Drives N-Channel High-Side and Low-Side MOSFETs
in a Synchronous Buck Configuration
Enhanced Upgrade to FAN5109
Direct Interface to FAN5029/FAN5182 and Other
Compatible PWM Controllers
12V High-Side and 12V Low-Side Drive
Internal Adaptive Shoot-Through Protection
Fast Rise and Fall Times
Switching Frequency Above 500kHz
OD Input for Output Disable – Allows Synchronization
with PWM Controller
SOIC-8 Package
TTL-Compatible Logic Inputs (New)
Description
The FAN5109B is a dual, high-frequency MOSFET
driver, specifically designed to drive N-channel power
MOSFETs in a synchronous-rectified buck converter.
These drivers, combined with a Fairchild multi-phase
pulse-width-modulated (PWM) controller and power
MOSFETs, form a complete core voltage regulator
solution for advanced microprocessors.
The FAN5109B drives the upper and lower MOSFET
gates of a synchronous buck regulator to 12V
GS
. The
output drivers have the capacity to efficiently switch
power MOSFETs at frequencies above 500KHz. The
circuit's adaptive shoot-through protection prevents both
MOSFETs from conducting simultaneously.
The FAN5109B is rated for operation from 0°C to +85°C
and is available in a low-cost SOIC-8 package.
Applications
Multi-Phase VRM/VRD Regulators for
Microprocessor Power
High-Current, High-Frequency DC/DC Converters
High-Power Modular Supplies
General-Purpose TTL Input MOSFET Drivers
Related Applications Notes
Application Note AN-6003, "Shoot-through" in
Synchronous Buck Converters
Ordering Information
Part Number
FAN5109BMX
Pb-Free
Yes
Operating
Temperature Range
0°C to 85°C
Package Packing Method Quantity Per Reel
SOIC-8
Tape and Reel
2500
Note:
1. Contact a Fairchild sales representative for availability of leaded (Pb) parts.
© 2006 Fairchild Semiconductor Corporation
FAN5109B Rev. 1.0.0
www.fairchildsemi.com
FAN5109B — Dual Bootstrapped 12V MOSFET Driver
Application Diagram
12V
4
VCC
D1
1
BOOT
Q1
C
VC C
PWM
2
8
HDRV
SW
Q2
C
BOOT
OD
3
Overlap
Protection
Circuit
L1
7
V
OU T
C
OUT
V
CC
5
LDRV
PGND
6
Figure 1. Typical Application
Block Diagram
V
CC
OD
VCC
BOOT
PWM
HDRV
t
Fall
Delay
t
Fall
Delay
V
CC
/3
1.2V
SW
1.2V
V
CC
LDRV
GND
Figure 2. Functional Block Diagram
© 2006 Fairchild Semiconductor Corporation
FAN5109B Rev. 1.0.0
www.fairchildsemi.com
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FAN5109B — Dual Bootstrapped 12V MOSFET Driver
Pin Configuration
BOOT
PWM
OD
VCC
1
2
3
4
FAN
5009
8
7
6
5
HDRV
SW
PGND
LDRV
Figure 3. Pin Assignments
Pin Definitions
Pin #
1
2
3
4
5
6
7
8
Name
BOOT
PWM
OD
Description
Bootstrap Supply Input.
Provides voltage supply to the high-side MOSFET driver. Connect
to the bootstrap capacitor (see the
Applications
section).
PWM Signal Input.
This pin accepts a logic-level PWM signal from the controller.
Output Disable.
When LOW, this pin disables FET switching (HDRV and LDRV are held
LOW). (Also referred to as OD#.)
Power Input.
+12V chip bias power. Bypass with a 1μF ceramic capacitor.
Low-Side Gate Drive Output.
Connect to the gate of low-side power MOSFET(s).
Power ground.
Connect directly to the source of the low-side MOSFET(s).
Switch Node Input.
Connect as shown in Figure 1. SW provides return for the high-side
bootstrapped driver and acts as a sense point for the adaptive shoot-through protection.
High-Side Gate Drive Output.
Connect to the gate of high-side power MOSFET(s).
VCC
LDRV
PGND
SW
HDRV
© 2006 Fairchild Semiconductor Corporation
FAN5109B Rev. 1.0.0
www.fairchildsemi.com
3 of 14
FAN5109B — Dual Bootstrapped 12V MOSFET Driver
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device
reliability. The absolute maximum ratings are stress ratings only.
Parameter
VCC and LDRV to GND
PWM and
OD
pins
SW to GND
BOOT to SW
BOOT to GND
HDRV
Continuous
LDRV
Transient (t=200ns)
(2)
(2)
Min.
-0.3
-0.3
Max.
15.0
5.5
15.0
25.0
15.0
17.0
30.0
38.0
V
BOOT
+0.3
V
CC
V
CC
+0.3
V
CC
+2.0
Unit
V
V
V
V
V
V
V
V
V
V
V
V
Continuous
Transient (t=100ns, f = 500kHz)
Continuous
Transient (t<20ns, f = 500kHz)
Continuous
Transient (t=100ns, f =500kHz)
(2)
-1.0
-5.0
-0.3
-2.0
-0.3
V
SW
-1.0
-0.5
-2.0
-2.0
Transient (t<20ns, f = 500kHz)
Note:
2. For transient derating beyond the levels indicated, refer to Figure 17 and Figure 18.
Thermal Information
Symbol
T
J
T
STG
T
L
T
VP
T
LI
P
D
θ
JC
θ
JA
Junction Temperature
Storage Temperature
Lead Soldering Temperature, 10 seconds
Vapor Phase, 60 seconds
Infrared, 15 seconds
Power Dissipation, T
A
= 25°C
Thermal Resistance, SO-8: Junction-to-Case
Thermal Resistance, SO-8: Junction-to-Ambient
40
140
Parameter
Min.
0
-65
Typ.
Max.
150
150
300
215
220
715
Unit
°C
°C
°C
°C
°C
mW
°C/W
°C/W
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
V
CC
T
A
T
J
Parameter
Supply Voltage
Ambient Temperature
Junction Temperature
Conditions
VCC to GND
Min.
10.0
0
0
Typ.
12.0
Max.
13.5
85
125
Unit
V
°C
°C
© 2006 Fairchild Semiconductor Corporation
FAN5109B Rev. 1.0.0
www.fairchildsemi.com
4 of 14
FAN5109B — Dual Bootstrapped 12V MOSFET Driver
Electrical Characteristics
V
CC
and V
LDRV
= 12V and T
A
= 25°C using the circuit in Figure 4, unless otherwise noted, each side. The “•” denotes
specifications that apply over the full operating temperature range.
Symbol
Input Supply
V
CC
I
CC
OD
Input
Parameter
V
CC
Voltage Range
V
CC
Current
Conditions
•
OD
= 0V
Min.
6.4
Typ.
12.0
2.5
Max.
13.5
4.0
Unit
V
mA
•
V
IH (OD)
V
IL (OD)
V
HYS(OD)
I
OD
t
pdl(OD)
t
pdh(OD)
PWM Input
V
IH(PWM)
V
IL(PWM)
V
HYS(PWM)
I
IL(PWM)
R
HUP
I
SOURCE(LDRV)
R
HDN
I
SINK(HDRV)
t
R(HDRV)
t
F(HDRV)
t
pdh(HDRV)
t
pdl(HDRV)
R
LUP
I
SOURCE(LDRV)
R
LDN
I
SINK(LDRV)
BG
th
t
R(LDRV)
t
F(LDRV)
t
pdh(LDRV)
t
pdl(LDRV)
t
pdh(LDF)
Input High Voltage
Input Low Voltage
Input Hysteresis
Input Current
Propagation Delay
(4)
•
•
•
OD
= 3.0V
2.0
0.8
250
–300
25
15
550
+300
40
30
V
V
mV
nA
ns
ns
V
0.8
V
mV
+1
2.5
2.0
1.1
2.5
25
15
40
25
2.0
40
25
55
40
2.6
1.2
1.6
30
25
30
25
1.5
3.3
µA
Ω
A
Ω
A
ns
ns
550
•
See Figure 5
Input High Voltage
Input Low Voltage
Input Hysteresis
Input Current
Output Resistance, Sourcing
Source Current
Sink Current
(4)
(4)
•
•
2.0
200
•
V
BOOT
– V
SW
= 12V
V
DS
= -10V
V
BOOT
– V
SW
= 12V
V
DS
= 10V
(4,6)
-1
High-Side Driver
Output Resistance, Sinking
Transition Times
See Figure 4
See Figure 6
Propagation Delay
(4,5)
Low-Side Driver
Output Resistance, Sourcing
Source Current
Sink Current
(4)
(4)
(4)
Ω
A
Ω
A
V
ns
ns
ns
ns
ns
V
DS
= -10V
V
DS
= 10V
1.0
See Figure 4
See Figure 6
2.5
0.9
2.5
1.2
20
15
20
15
140
Output Resistance, Sinking
Bottom Gate Threshold
Transition Times
(4,6)
Propagation Delay
(4,5)
See
Adaptive Gate Drive
Circuit Description
Notes:
3. Limits at operating temperature extremes are guaranteed by design, characterization, and statistical quality control.
4. Specifications guaranteed by design and characterization (not production tested).
5. For propagation delays, t
pdh
refers to low-to-high signal transition. t
pdl
refers to high-to-low signal transition.
6. Transition times are defined for 10% and 90% of DC values.
© 2006 Fairchild Semiconductor Corporation
FAN5109B Rev. 1.0.0
www.fairchildsemi.com
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