Integrated
Circuit
Systems, Inc.
ICS951411
System Clock Chip for ATI RS400 P4
TM
-based Systems
Recommended Application:
ATI RS400 systems using Intel P4
TM
processors
Output Features:
•
6 - Pairs of SRC/PCI-Express clocks
•
2 - Pairs of ATIG (SRC/PCI Express*) clocks
•
3 - Pairs of Intel P4 clocks
•
3 - 14.318 MHz REF clocks
•
1 - 48MHz USB clock
•
1 - 33 MHz PCI clock seed
Key Specifications:
•
CPU outputs cycle-cycle jitter < 85ps
•
SRC output cycle-cycle jitter <125ps
•
PCI outputs cycle-cycle jitter < 250ps
•
+/- 300ppm frequency accuracy on CPU & SRC clocks
Features/Benefits:
•
2- Programmable Clock Request pins for SRC clocks
•
Supports CK410 or CK409 frequency table mapping
•
Spread Spectrum for EMI reduction
•
Outputs may be disabled via SMBus
•
External crystal load capacitors for maximum
frequency accuracy
Functionality - (CK410# = 0)
CPU
SRC
PCI
FS_C
1
FS_B
1
FS_A
1
MHz
MHz
MHz
0
266.66 100.00 33.33
0
1
133.33 100.00 33.33
0
0
200.00 100.00 33.33
1
1
166.66 100.00 33.33
0
333.33 100.00 33.33
0
1
100.00 100.00 33.33
1
0
400.00 100.00 33.33
1
RESERVED
1
Functionality - (CK410# = 1)
FS_C
1
CPU
Byte6 FS_B
1
FS_A
1
MHz
bit5
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
100.00
200.00
133.33
166.67
200.00
400.00
266.67
333.33
SRC
MHz
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
PCI
MHz
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
Pin Configuration
REF
MHz
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
U
SB
MHz
48.000
48.000
48.000
48.000
48.000
48.000
48.000
48.000
0
1
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
48.000
48.000
48.000
48.000
48.000
48.000
48.000
48.000
1. FS_C, FS_B and FS_A are low-threshold inputs. Please see the V
IL_FS
and V
IH_FS
specifications in the Input/Supply/Common Output Parameters Table for correct values.
Note:
Pins preceeded by '**' have a 120 Kohm Internal Pull Down resistor
Pins preceeded by '*' have a 120 Kohm Internal Pull Up resistor
56-pin SSOP & TSSOP
0891E—03/07/05
*Other names and brands may be claimed as the property of others.
ICS951411
REF
MHz
U
SB
MHz
X1
X2
VDD48
USB_48MHz
GND
VTT_PWRGD#/PD
SCLK
SDATA
**FS_C
**CLKREQA#
**CLKREQB#
SRCCLKT7
SRCCLKC7
VDDSRC
GNDSRC
SRCCLKT6
SRCCLKC6
SRCCLKT5
SRCCLKC5
GNDSRC
VDDSRC
SRCCLKT4
SRCCLKC4
SRCCLKT3
SRCCLKC3
GNDSRC
ATIGCLKT1
ATIGCLKC1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
VDDREF
GND
**FS_A/REF0
**FS_B/REF1
**TEST_SEL/REF2
VDDPCI
**CK410#/PCICLK0
GNDPCI
*CPU_STOP#
CPUCLKT0
CPUCLKC0
VDDCPU
GNDCPU
CPUCLKT1
CPUCLKC1
CPUCLKT2_ITP
CPUCLKC2_ITP
VDDA
GNDA
IREF
GNDSRC
VDDSRC
SRCCLKT0
SRCCLKC0
VDDATI
GNDATI
ATIGCLKT0
ATIGCLKC0
Integrated
Circuit
Systems, Inc.
ICS951411
Pin Description
PIN #
1
2
3
4
5
6
7
8
9
10
PIN NAME
X1
X2
VDD48
USB_48MHz
GND
VTT_PWRGD#/PD
SCLK
SDATA
**FS_C
**CLKREQA#
PIN
TYPE
IN
OUT
PWR
OUT
PWR
IN
IN
I/O
IN
IN
DESCRIPTION
Crystal input, Nominally 14.318MHz.
Crystal output, Nominally 14.318MHz
Power pin for the 48MHz output.3.3V
48.00MHz USB clock
Ground pin.
Vtt_PwrGd# is an active low input used to determine when latched inputs are
ready to be sampled. PD is an asynchronous active high input pin used to put
the device into a low power state. The internal clocks, PLLs and the crystal
oscillator are stopped.
Clock pin of SMBus circuitry, 5V tolerant.
Data pin for SMBus circuitry, 5V tolerant.
Frequency select latch input pin
Output enable for PCI Express (SRC) outputs. SMBus selects which outputs
are controlled.
0 = enabled, 1 = tri-stated
Output enable for PCI Express (SRC) outputs. SMBus selects which outputs
are controlled.
0 = enabled, 1 = tri-stated
True clock of differential SRC clock pair.
Complement clock of differential SRC clock pair.
Supply for SRC clocks, 3.3V nominal
Ground pin for the SRC outputs
True clock of differential SRC clock pair.
Complement clock of differential SRC clock pair.
True clock of differential SRC clock pair.
Complement clock of differential SRC clock pair.
Ground pin for the SRC outputs
Supply for SRC clocks, 3.3V nominal
True clock of differential SRC clock pair.
Complement clock of differential SRC clock pair.
True clock of differential SRC clock pair.
Complement clock of differential SRC clock pair.
Ground pin for the SRC outputs
True clock of differential SRC clock pair.
Complementary clock of differential SRC clock pair.
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
**CLKREQB#
SRCCLKT7
SRCCLKC7
VDDSRC
GNDSRC
SRCCLKT6
SRCCLKC6
SRCCLKT5
SRCCLKC5
GNDSRC
VDDSRC
SRCCLKT4
SRCCLKC4
SRCCLKT3
SRCCLKC3
GNDSRC
ATIGCLKT1
ATIGCLKC1
IN
OUT
OUT
PWR
PWR
OUT
OUT
OUT
OUT
PWR
PWR
OUT
OUT
OUT
OUT
PWR
OUT
OUT
0891E—03/07/05
2
Integrated
Circuit
Systems, Inc.
ICS951411
Pin Description (Continued)
PIN #
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
PIN NAME
ATIGCLKC0
ATIGCLKT0
GNDATI
VDDATI
SRCCLKC0
SRCCLKT0
VDDSRC
GNDSRC
IREF
GNDA
VDDA
CPUCLKC2_ITP
CPUCLKT2_ITP
CPUCLKC1
CPUCLKT1
GNDCPU
VDDCPU
CPUCLKC0
CPUCLKT0
*CPU_STOP#
GNDPCI
**CK410#/PCICLK0
VDDPCI
**TEST_SEL/REF2
**FS_B/REF1
**FS_A/REF0
GND
VDDREF
PIN
TYPE
OUT
OUT
PWR
PWR
OUT
OUT
PWR
PWR
DESCRIPTION
Complementary clock of differential SRC clock pair.
True clock of differential SRC clock pair.
Ground for ATI Gclocks, nominal 3.3V
Power supply ATI Gclocks, nominal 3.3V
Complement clock of differential SRC clock pair.
True clock of differential SRC clock pair.
Supply for SRC clocks, 3.3V nominal
Ground pin for the SRC outputs
This pin establishes the reference current for the differential current-mode
OUT output pairs. This pin requires a fixed precision resistor tied to ground in order
to establish the appropriate current. 475 ohms is the standard value.
PWR Ground pin for the PLL core.
PWR 3.3V power for the PLL core.
Complementary clock of differential pair CPU outputs. These are current mode
OUT
outputs. External resistors are required for voltage bias.
True clock of differential pair CPU outputs. These are current mode outputs.
OUT
External resistors are required for voltage bias.
Complementary clock of differential pair CPU outputs. These are current mode
OUT
outputs. External resistors are required for voltage bias.
True clock of differential pair CPU outputs. These are current mode outputs.
OUT
External resistors are required for voltage bias.
PWR Ground pin for the CPU outputs
PWR Supply for CPU clocks, 3.3V nominal
Complementary clock of differential pair CPU outputs. These are current mode
OUT
outputs. External resistors are required for voltage bias.
True clock of differential pair CPU outputs. These are current mode outputs.
OUT
External resistors are required for voltage bias.
IN Stops all CPUCLK, except those set to be free running clocks
PWR Ground pin for the PCI outputs
FS Table select latch input pin / 3.3V PCI clock output.
I/O
0 = CK410 FS Table, 1 = CK409 FS Table
PWR Power supply for PCI clocks, nominal 3.3V
I/O
I/O
I/O
PWR
PWR
TEST_SEL: latched input to select TEST MODE / 14.318 MHz reference clock.
1 = All outputs are CK410 REF/N test mode
0 = All outputs behave normally.
Frequency select latch input pin / 14.318 MHz reference clock.
Frequency select latch input pin / 14.318 MHz reference clock.
Ground pin.
Ref, XTAL power supply, nominal 3.3V
0891E—03/07/05
3
Integrated
Circuit
Systems, Inc.
ICS951411
General Description
ICS951411
provides a single-chip clocking solution for the ATI RS400-based systems using the latest Intel P4 processors.
ICS951411
is driven with a 14.318MHz crystal. It generates CPU outputs up to 400MHz and also provides highly accurate
SRC clocks for PCI Express support. Two Clock Request pins are provided for Express-Card
TM
support.
Block Diagram
REF(2:0)
X1
X2
XTAL
OSC.
FIXED PLL
DIVIDER
USB_48MHz
PCICLK0
ATIGCLK(1:0)
MAIN PLL
DIVIDERS
SRCCLK(7:3,0)
CPUCLK(2:0)
CK410#
FS(C:A)
CLKREQA#
CLKREQB#
CPU_STOP#
VTT_PWRGD#/PD
SDATA
SCLK
CONTROL
LOGIC
IREF
Power Groups
Pin Number
VDD
GND
56
55
51
49
45
44
14, 21, 35 15, 20, 26, 36
32
31
39
38
3
5
Description
Xtal, REF
PCICLK output
CPUCLK Outputs
SRCCLK outputs
ATIGCLK outputs
Analog, CPU PLL
USB_48MHz output
0891E—03/07/05
4
Integrated
Circuit
Systems, Inc.
ICS951411
General SMBus serial interface information for the ICS951411
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address D2
(H)
ICS clock will
acknowledge
Controller (host) sends the begining byte location = N
ICS clock will
acknowledge
Controller (host) sends the data byte count = X
ICS clock will
acknowledge
Controller (host) starts sending
Byte N through
Byte N + X -1
(see Note 2)
• ICS clock will
acknowledge
each byte
one at a time
• Controller (host) sends a Stop bit
•
•
•
•
•
•
•
•
How to Read:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Controller (host) will send start bit.
Controller (host) sends the write address D2
(H)
ICS clock will
acknowledge
Controller (host) sends the begining byte
location = N
ICS clock will
acknowledge
Controller (host) will send a separate start bit.
Controller (host) sends the read address D3
(H)
ICS clock will
acknowledge
ICS clock will send the data byte count = X
ICS clock sends
Byte N + X -1
ICS clock sends
Byte 0 through byte X (if X
(H)
was written to byte 8)
.
Controller (host) will need to acknowledge each byte
Controllor (host) will send a not acknowledge bit
Controller (host) will send a stop bit
Index Block Write Operation
Controller (Host)
starT bit
T
Slave Address D2
(H)
WR
WRite
Beginning Byte = N
ACK
Data Byte Count = X
ACK
Beginning Byte N
ACK
X Byte
ICS (Slave/Receiver)
Index Block Read Operation
Controller (Host)
T
starT bit
Slave Address D2
(H)
WR
WRite
Beginning Byte = N
ACK
RT
Repeat starT
Slave Address D3
(H)
RD
ReaD
ACK
Data Byte Count = X
ACK
Beginning Byte N
ACK
X Byte
ICS (Slave/Receiver)
ACK
ACK
Byte N + X - 1
ACK
P
stoP bit
Byte N + X - 1
N
P
Not acknowledge
stoP bit
0891E—03/07/05
5
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