EP2S15F484C5 datasheet, PDF - EEWORLD Datasheet

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EP2S15F484C5: DescriptionIC FPGA 342 I/O 484FBGA; CategoryProgrammable logic devices Programmable logic; File Size2MB，182 Pages; ManufacturerIntel; Websitehttp://www.intel.com/

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EP2S15F484C5 Overview

IC FPGA 342 I/O 484FBGA

EP2S15F484C5 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
package instruction	BGA, BGA484,22X22,40
Reach Compliance Code	compliant
ECCN code	3A991
maximum clock frequency	640 MHz
Combined latency of CLB-Max	5.962 ns
JESD-30 code	S-PBGA-B484
JESD-609 code	e0
length	23 mm
Humidity sensitivity level	3
Configurable number of logic blocks	6240
Number of entries	342
Number of logical units	15600
Output times	334
Number of terminals	484
Maximum operating temperature	85 °C
Minimum operating temperature
organize	6240 CLBS
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Encapsulate equivalent code	BGA484,22X22,40
Package shape	SQUARE
Package form	GRID ARRAY
Peak Reflow Temperature (Celsius)	220
power supply	1.2,1.5/3.3,3.3 V
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
Certification status	Not Qualified
Maximum seat height	3.5 mm
Maximum supply voltage	1.25 V
Minimum supply voltage	1.15 V
Nominal supply voltage	1.2 V
surface mount	YES
technology	CMOS
Temperature level	OTHER
Terminal surface	TIN LEAD
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	30
width	23 mm
Base Number Matches	1

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Package Information Datasheet for

Mature Altera Devices

DS-PKG-16.8

This datasheet provides package and thermal resistance information for mature

Altera

devices. Package information includes the ordering code reference, package

acronym, leadframe material, lead finish (plating), JEDEC outline reference, lead

coplanarity, weight, moisture sensitivity level, and other special information. The

thermal resistance information includes device pin count, package name, and

resistance values.

This datasheet includes the following sections:

■

“Device and Package Cross Reference” on page 1

“Thermal Resistance” on page 23

“Package Outlines” on page 44

For more package and thermal resistance information about Altera devices that are

not listed in this datasheet, refer to the

Package and Thermal Resistance

page of the

Altera website.

For information about trays, tubes, and dry packs, refer to

AN 71: Guidelines for

Handling J-Lead, QFP, and BGA Devices.

RoHS-compliant devices are compatible with leaded-reflow temperatures. For more

information, refer to

Altera’s RoHS-Compliant Devices

literature page.

Device and Package Cross Reference

Table 2

through

Table 22

lists the device, package type, and number of pins for each

Altera device listed in this datasheet. Altera devices listed in this datasheet are

available in the following packages:

■

Ball-Grid Array (BGA)

Ceramic Pin-Grid Array (PGA)

FineLine BGA (FBGA)

Hybrid FineLine BGA (HBGA)

Plastic Dual In-Line Package (PDIP)

Plastic Enhanced Quad Flat Pack (EQFP)

Plastic J-Lead Chip Carrier (PLCC)

Plastic Quad Flat Pack (PQFP)

Power Quad Flat Pack (RQFP)

Thin Quad Flat Pack (TQFP)

Ultra FineLine BGA (UBGA)

Altera Corporation

Package Information Datasheet for Mature Altera Devices

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