ZL30155
Dual Channel Universal Clock Translator
Short Form Data Sheet
January 2012
Features
•
•
•
•
•
Two independent clock channels
Programmable synthesizers generate any clock-
rate from 1 kHz to 750 MHz
Two precision synthesizers generate clocks with
jitter below 0.7 ps RMS for 10 G PHYs
Programmable digital PLLs synchronize to any
clock rate from 1 kHz to 750 MHz
Flexible two-stage architecture translates between
arbitrary data rates, line coding rates and FEC
rates
Digital PLLs filter jitter from 14 Hz, 28 Hz, 56 Hz,
112 Hz, 224 Hz, 448 Hz or 896 Hz
Automatic hitless reference switching and digital
holdover on reference fail
Four reference inputs configurable as single ended
or differential
Eight LVPECL outputs and four LVCMOS outputs
Ordering Information
ZL30155GGG
100 Pin LBGA
ZL30155GGG2 100 Pin LBGA*
*Pb Free Tin/Silver/Copper
-40
o
C to +85
o
C
Trays
Trays
•
•
Operates from a single crystal resonator or clock
oscillator
Configurable via SPI/I2C interface
Applications
•
•
•
•
10 Gigabit line cards
Synchronous Ethernet, 10 GBASE-R and
10 GBASE-W
OTN multiplexers and transponders
SONET/SDH, Fibre Channel, XAUI
•
•
•
•
Figure 1 - Functional Block Diagram
1
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