24AA044
4K I
2
C
™
Serial EEPROM
Device Selection Table
Part
Number
24AA044
Note 1:
V
CC
Range
1.7V-5.5V
Max Clock
Frequency
1 MHz
(1)
Temp.
Range
I, E
Description:
The Microchip Technology Inc. 24AA044 is a 4 Kbit
Serial Electrically Erasable PROM with a voltage
range of 1.7V to 5.5V. The device is organized as two
blocks of 256 x 8-bit memory with a 2-wire serial
interface. Low-current design permits operation with
standby and active currents of only 1
A
and 400
A,
respectively. The device has a page write capability for
up to 16 bytes of data. Functional address lines allow
the connection of up to four 24AA044 devices on the
same bus for up to 16K bits of contiguous EEPROM
memory. The device is available in the standard 8-pin
PDIP, 8-pin SOIC (3.90 mm), TSSOP, 2x3 UDFN and
MSOP packages.
400 kHz for 1.8V
≤
V
CC
< 2.2V
100 kHz for V
CC
< 1.8V
Features:
• Single Supply with Operation from 1.7V to 5.5V
• Low-Power CMOS Technology:
- Read current 400
A,
max
- Standby current 1
A,
max at 85°C
• 2-Wire Serial Interface, I
2
C™ Compatible
• Cascadable up to Four Devices
• Schmitt Trigger Inputs for Noise Suppression
• Output Slope Control to Eliminate Ground Bounce
• 1 MHz, 400 kHz, and 100 kHz Clock Compatibility
• Page Write Time 5 ms Maximum
• Self-timed Erase/Write Cycle
• 16-Byte Page Write Buffer
• Hardware Write-Protect
• ESD Protection >4,000V
• More than 1 Million Erase/Write Cycles
• Data Retention >200 Years
• Factory Programming Available
• Packages include 8-lead PDIP, SOIC, TSSOP,
UDFN and MSOP
• RoHS Compliant
• Temperature Ranges:
- Industrial (I): -40°C to +85°C
- Automotive (E): -40°C to +125°C
Package Types
PDIP/SOIC/TSSOP/MSOP
NC
A1
A2
V
SS
1
2
3
4
8
7
6
5
V
CC
WP
SCL
SDA
NC 1
A1 2
A2 3
V
SS
4
UDFN
8 V
CC
7 WP
6 SCL
5 SDA
Block Diagram
A1A2
WP
HV Generator
I/O
Control
Logic
Memory
Control
Logic
XDEC
EEPROM
Array
SDA SCL
V
CC
V
SS
Write-Protect
Circuitry
YDEC
Sense Amp.
R/W Control
2014 Microchip Technology Inc.
DS20005286A-page 1
24AA044
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
(†)
V
CC
.............................................................................................................................................................................6.5V
All inputs and outputs w.r.t. V
SS
................................................................................................................... -0.3V to 6.5V
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature with power applied ................................................................................................-40°C to +125°C
ESD protection on all pins
4 kV
† NOTICE:
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. These are stress ratings only and functional operation of the device at these or any other conditions above
those indicated in the operation sections of the specifications is not implied. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
TABLE 1-1:
DC SPECIFICATIONS
Industrial (I):
T
A
= -40°C to +85°C, V
CC
= +1.7V to +5.5V
Automotive (E): T
A
= -40°C to +125°C, V
CC
= +1.7V to +5.5V
Characteristic
A1, A2, SCL, SDA and WP
pins
High-level input voltage
Low-level input voltage
Hysteresis of Schmitt
Trigger inputs
Low-level output voltage
Input leakage current
Output leakage current
Min.
—
0.7 V
CC
—
0.05 V
CC
—
—
—
—
—
—
Standby current
—
—
Max.
—
V
CC
+ 0.5
0.3 V
CC
0.2 V
CC
—
0.40
±1
±1
10
3
400
1
5
Units
—
V
V
V
V
V
A
A
pF
mA
A
A
A
—
—
V
CC
≥
2.5V
V
CC
< 2.5V
(Note)
I
OL
= 3.0 mA, V
CC
= 2.5V
V
IN
= V
SS
or V
CC
V
OUT
= V
SS
or V
CC
V
CC
= 5.5V
(Note)
T
A
= 25°C, F
CLK
= 1 MHz
V
CC
= 5.5V
V
CC
= 5.5V, SCL = 1 MHz
Industrial
Automotive
SDA, SCL = V
CC
A1, A2, WP = V
SS
Conditions
DC CHARACTERISTICS
Param.
No.
Symbol
—
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
V
IH
V
IL
V
HYS
V
OL
I
LI
I
LO
C
IN
, C
OUT
Pin capacitance
(all inputs/outputs)
I
CC
write
I
CC
read
I
CCS
Operating current
Note:
This parameter is periodically sampled and not 100% tested.
DS20005286A-page 2
2014 Microchip Technology Inc.
24AA044
TABLE 1-2:
AC CHARACTERISTICS
Industrial (I):
T
A
= -40°C to +85°C, V
CC
= +1.7V to +5.5V
Automotive (E): T
A
= -40°C to +125°C, V
CC
= +1.7V to +5.5V
Characteristic
Min.
Max.
Units
Conditions
AC CHARACTERISTICS
Param.
No.
Symbol
1
F
CLK
Clock frequency
—
—
—
4000
600
500
4700
1300
500
—
—
—
—
—
—
4000
600
250
4700
600
250
0
250
100
100
4000
600
250
4000
600
600
4700
1300
1300
—
—
—
4700
1300
500
—
—
1M
100
400
1000
—
—
—
—
—
—
1000
300
300
300
300
100
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
3500
900
400
—
—
50
5
—
kHz
1.7V
V
CC
< 1.8V
1.8V
V
CC
< 2.2V
2.2V
V
CC
< 5.5V
1.7V
V
CC
< 1.8V
1.8V
V
CC
< 2.2V
2.2V
V
CC
< 5.5V
1.7V
V
CC
< 1.8V
1.8V
V
CC
< 2.2V
2.2V
V
CC
< 5.5V
1.7V
V
CC
< 1.8V
1.8V
V
CC
< 2.2V
2.2V
V
CC
< 5.5V
1.7V
V
CC
< 1.8V
1.8V
V
CC
< 2.2V
2.2V
V
CC
< 5.5V
1.7V
V
CC
< 1.8V
1.8V
V
CC
< 2.2V
2.2V
V
CC
< 5.5V
1.7V
V
CC
< 1.8V
1.8V
V
CC
< 2.2V
2.2V
V
CC
< 5.5V
(Note
2)
1.7V
V
CC
< 1.8V
1.8V
V
CC
< 2.2V
2.2V
V
CC
< 5.5V
1.7V
V
CC
< 1.8V
1.8V
V
CC
< 2.2V
2.2V
V
CC
< 5.5V
1.7V
V
CC
< 1.8V
1.8V
V
CC
< 2.2V
2.2V
V
CC
< 5.5V
1.7V
V
CC
< 1.8V
1.8V
V
CC
< 2.2V
2.2V
V
CC
< 5.5V
1.7V
V
CC
< 1.8V
1.8V
V
CC
< 2.2V
2.2V
V
CC
< 5.5V
1.7V
V
CC
< 1.8V
1.8V
V
CC
< 2.2V
2.2V
V
CC
< 5.5V
(Note
1)
—
Page mode, 25°C, V
CC
= 5.5V
(Note
3)
2
T
HIGH
Clock high time
ns
3
T
LOW
Clock low time
ns
4
T
R
SDA and SCL rise time
(Note
1)
ns
5
T
F
SDA and SCL fall time
(Note
1)
ns
6
T
HD
:
STA
Start condition hold time
ns
7
T
SU
:
STA
Start condition setup time
ns
8
9
T
HD
:
DAT
T
SU
:
DAT
Data input hold time
Data input setup time
ns
ns
10
T
SU
:
STO
Stop condition setup time
ns
11
T
SU
:
WP
WP setup time
ns
12
T
HD
:
WP
WP hold time
ns
13
T
AA
Output valid from clock
(Note
2)
ns
14
T
BUF
Bus free time: Time the bus must
be free before a new transmission
can start
Input filter spike suppression
(SDA and SCL pins)
Write cycle time (byte or page)
Endurance
ns
15
16
17
T
SP
T
WC
—
ns
ms
cycles
Note 1:
Not 100% tested.
2:
As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum
200 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
3:
This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please
consult the Total Endurance™ Model which can be obtained from Microchip’s web site at www.microchip.com.
2014 Microchip Technology Inc.
DS20005286A-page 3
24AA044
FIGURE 1-1:
BUS TIMING DATA
5
2
D3
4
SCL
SDA
In
7
6
15
3
8
9
10
13
SDA
Out
(protected)
(unprotected)
14
WP
11
12
DS20005286A-page 4
2014 Microchip Technology Inc.
24AA044
2.0
PIN DESCRIPTIONS
Pin Function Table
Name
NC
A1
A2
V
SS
SDA
SCL
WP
V
CC
PDIP
1
2
3
4
5
6
7
8
SOIC
1
2
3
4
5
6
7
8
TSSOP
1
2
3
4
5
6
7
8
UDFN
1
2
3
4
5
6
7
8
MSOP
1
2
3
4
5
6
7
8
Description
Not Connected
Chip Address Input
Chip Address Input
Ground
Serial Address/Data I/O
Serial Clock
Write-Protect Input
+1.7 to 5.5V Power Supply
2.1
Serial Data (SDA)
2.5
Noise Protection
SDA is a bidirectional pin used to transfer addresses
and data into and out of the device. It is an open-drain
terminal; therefore, the SDA bus requires a pull-up
resistor to V
CC
(typical 10 k for 100 kHz, 2 k for
400 kHz and 1 MHz).
For normal data transfer, SDA is allowed to change
only during SCL low. Changes during SCL high are
reserved for indicating the Start and Stop conditions.
The 24AA044 employs a V
CC
threshold detector circuit
which disables the internal erase/write logic if the V
CC
is below 1.35V at nominal conditions.
The SCL and SDA inputs have Schmitt Trigger and
filter circuits which suppress noise spikes to assure
proper device operation, even on a noisy bus.
3.0
FUNCTIONAL DESCRIPTION
2.2
Serial Clock (SCL)
The SCL input is used to synchronize the data transfer
from and to the device.
2.3
Chip Address Inputs (A1, A2)
The levels on the A1 and A2 inputs are compared with
the corresponding bits in the slave address. The chip is
selected if the compare is true.
Up to four 24AA044 devices may be connected to the
same bus by using different Chip Select bit combina-
tions. These inputs must be connected to either V
CC
or
V
SS
.
The 24AA044 supports a bidirectional, 2-wire bus
and data transmission protocol. A device that sends
data onto the bus is defined as transmitter, while a
device receiving data is defined as receiver. The bus
has to be controlled by a master device that gener-
ates the Serial Clock (SCL), controls the bus access
and generates the Start and Stop conditions, while
the 24AA044 works as slave. Both master and slave
can operate as transmitter or receiver, but the master
device determines which mode is activated.
2.4
Write-Protect (WP)
WP is the hardware write-protect pin. It must be tied to
V
CC
or V
SS
. If tied to Vcc, hardware write protection is
enabled. If WP is tied to Vss, the hardware write
protection is disabled.
2014 Microchip Technology Inc.
DS20005286A-page 5
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