BUK7210-55B
N-channel TrenchMOS standard level FET
Rev. 01 — 11 December 2008
Product data sheet
1. Product profile
1.1 General description
Standard level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using
Nexperia
High-Performance Automotive (HPA) TrenchMOS technology.
This product has been designed and qualified to the appropriate AEC standard for use
in automotive critical applications.
1.2 Features and benefits
185 °C rated
Q101 compliant
Standard level compatible
Very low on-state resistance
1.3 Applications
12 V and 24 V loads
Automotive systems
General purpose power switching
Motors, lamps and solenoids
1.4 Quick reference data
Table 1.
V
DS
I
D
Quick reference
Conditions
V
GS
= 10 V; T
mb
= 25 °C;
see
Figure 1;
see
Figure 3;
V
GS
= 10 V; I
D
= 25 A;
T
j
= 25 °C; see
Figure 10;
see
Figure 9
I
D
= 75 A; V
sup
≤
55 V;
R
GS
= 50
Ω;
V
GS
= 10 V;
T
j(init)
= 25 °C; unclamped
inductive load
[1]
Min
-
-
Typ
-
-
Max
55
75
Unit
V
A
drain-source voltage T
j
≥
25 °C; T
j
≤
185 °C
drain current
Symbol Parameter
Static characteristics
R
DSon
drain-source
on-state resistance
-
8.5
10
mΩ
Avalanche ruggedness
E
DS(AL)S
non-repetitive
drain-source
avalanche energy
-
-
173
mJ
[1]
Continuous current is limited by package.
Nexperia
BUK7210-55B
N-channel TrenchMOS standard level FET
2. Pinning information
Table 2.
Pin
1
2
3
mb
Pinning information
Symbol
G
D
S
D
Description
gate
drain
source
mounting base; connected to
drain
2
1
3
Simplified outline
[1]
mb
Graphic symbol
D
G
mbb076
S
SOT428
(SC-63; DPAK)
[1]
It is not possible to make connection to pin 2 of the SOT428 package.
3. Ordering information
Table 3.
Ordering information
Type number
Package
Name
Description
BUK7210-55B
SC-63;
plastic single-ended surface-mounted package (DPAK); 3 leads (one
DPAK
lead cropped)
Version
SOT428
BUK7210-55B_1
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 01 — 11 December 2008
2 of 14
Nexperia
BUK7210-55B
N-channel TrenchMOS standard level FET
4. Limiting values
Table 4.
Symbol
V
DS
V
DGR
V
GS
I
D
Limiting values
Parameter
drain-source voltage
drain-gate voltage
gate-source voltage
drain current
T
mb
= 25 °C; V
GS
= 10 V; see
Figure 1;
see
Figure 3;
T
mb
= 100 °C; V
GS
= 10 V; see
Figure 1
T
mb
= 25 °C; V
GS
= 10 V; see
Figure 1;
see
Figure 3;
I
DM
P
tot
T
stg
T
j
I
S
I
SM
E
DS(AL)S
peak drain current
total power dissipation
storage temperature
junction temperature
source current
peak source current
T
mb
= 25 °C;
T
mb
= 25 °C;
t
p
≤
10 µs; pulsed; T
mb
= 25 °C
Avalanche ruggedness
non-repetitive
I
D
= 75 A; V
sup
≤
55 V; R
GS
= 50
Ω;
V
GS
= 10 V;
drain-source avalanche T
j(init)
= 25 °C; unclamped inductive load
energy
[1]
[2]
[3]
Current is limited by power dissipation chip rating.
Continuous current is limited by package.
Current is limited by power dissipation chip rating.
In accordance with the Absolute Maximum Rating System (IEC 60134).
Conditions
T
j
≥
25 °C; T
j
≤
185 °C
R
GS
= 20 kΩ; 25 °C
≤
T
j
≤
185 °C
[1]
Min
-
-
-20
-
-
[2]
-
-
-
-55
-55
[2]
[3]
-
-
-
-
Max
55
55
20
89.6
65.5
75
335
167
185
185
75
89.6
335
173
Unit
V
V
V
A
A
A
A
W
°C
°C
A
A
A
mJ
T
mb
= 25 °C; t
p
≤
10 µs; pulsed
T
mb
= 25 °C; see
Figure 2
Source-drain diode
BUK7210-55B_1
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 01 — 11 December 2008
3 of 14
Nexperia
BUK7210-55B
N-channel TrenchMOS standard level FET
100
I
D
(A)
75
003aac284
Capped at 75A due to package
120
P
der
(%)
80
03no96
50
40
25
0
0
50
100
150
T
mb
(°C)
200
0
0
50
100
150
200
T
mb
(°C)
Fig 1.
Normalized continuous drain current as a
function of mounting base temperature
Fig 2.
Normalized total power dissipation as a
function of mounting base temperature
003aac272
10
3
I
D
(A)
Limit R
DSon
= V
DS
/ I
D
10
2
t
p
= 10
µ
s
100
µ
s
Capped at 75 A due to package
DC
1 ms
10 ms
100 ms
10
1
1
10
V
DS
(V)
10
2
Fig 3.
Safe operating area; continuous and peak drain currents as a function of drain-source voltage
BUK7210-55B_1
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 01 — 11 December 2008
4 of 14
Nexperia
BUK7210-55B
N-channel TrenchMOS standard level FET
5. Thermal characteristics
Table 5.
Symbol
R
th(j-mb)
Thermal characteristics
Parameter
Conditions
Min
-
Typ
-
Max
0.95
Unit
K/W
thermal resistance from see
Figure 4
junction to mounting
base
thermal resistance from Mounted on a printed circuit board; vertical
junction to ambient
in still air.; minimum footprint
R
th(j-a)
-
75
-
K/W
1
Z
th (j-mb)
(K/W)
d = 0.5
0.2
10
-1
0.1
0.05
0.02
10
-2
P
003aac273
δ
=
single shot
t
p
T
t
p
T
t
10
-3
1e-6
10
-5
10
-4
10
-3
10
-2
10
-1
t
p
(s)
1
Fig 4.
Transient thermal impedance from junction to mounting base as a function of pulse duration
BUK7210-55B_1
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 01 — 11 December 2008
5 of 14
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