NCP3901
Dual Input, Single Output
Power Source Multiplexer
The NCP3901 integrated circuit is a dual input, single output power
source multiplexer. It is optimized for multiplexing 2 different
charging inputs to feed a single input battery charger. To address all
types of applications, the device is able to support autonomous and
slave modes of operation. Reverse USB on−the−go is fully supported.
Features
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3 A DC Minimum Current through Power Paths
Reverse 5 V OTG Support through VINA Path
Maximum 20 V Over Voltage Threshold
28 V Absolute Maximum Voltage on VINA
Compliance with IEC61000−4−5 at 100 V for VINA
Indication of Presence of Second Input
Autonomous Priority Selection and Switch Over Lock
Small Footprint: 3.1 x 1.65 mm WLCSP28 0.4 mm Pitch
30 ms Minimum Break−before−make Time
This is a Pb−Free Device
MARKING
DIAGRAM
3901
AWLYWW
G
3901= NCP3901
A
= Assembly Location
WL = Wafer Lot
Y
= Year
WW = Work Week
G
= Pb−Free Package
WLCSP28
FCC SUFFIX
CASE 567KR
Typical Applications
ORDERING INFORMATION
See detailed ordering, marking and shipping information on
page 11 of this data sheet.
Handheld Devices
Tablets
Smart Phone
PDAs
VINA
VINA
VINA
PRIMARY
CHARGING
SOURCE
(i.e. USB)
1 uF
VINA
VINA
VINA
VINA
ESD
P ROTE CTIO N
I EC61 000−4−
5
1. 2/50u s −10 /700u s
>1 00V
CHANNEL 1 BACK
TO BACK MOSFETS
OUT
OUT
OUT
OUT
OUTPUT
DICHARGE
4.7uF
OUT
OUT
4.7 uF
Battery /
System
HV SBC
Li−
Ion
SYSTEM
OUT
VOVLO
IN1 PROTECTED SENSE
OUT
VUVLO
VINA_S
OTG_EN / VINA_EN
GND
GND
GND
GND
GND
INTERNAL POWER
SUPPLY /
REFERENCE
VOLTAGE
1.8V
CTRL
LDO
LOGIC CONTROL
MODE
VOVLO
E SD
P RO TECTI ON
1. 8V
1 uF
DRIVERS
FLAG / VINB_EN
VUVLO
FLAG
SECONDARY
CHARGING
SOURCE
(i.e. A4WP,
Dock)
VINB
VINB
VINB
VINB
CHANNEL 2 BACK
TO BACK MOSFETS
NCP3901
Figure 1. Typical Application Circuit
©
Semiconductor Components Industries, LLC, 2016
1
September, 2016 − Rev. 2
Publication Order Number:
NCP3901/D
NCP3901
Table 1. PIN FUNCTIONAL DESCRIPTION
Pin
A1
A2
A3
A4
A5
A6
A7
C4
B5
B6
B7
C5
C6
C7
B1
B2
B3
C2
C3
D4
D5
D6
D7
C1
D1
B4
D2
D3
MODE
CRTL
VINA_S
VINA_EN/OTG_EN
VINB_EN/FLAG
DIGITAL INPUT
DIGITAL INPUT
ANALOG OUTPUT
DIGITAL INPUT
DIGITAL INPUT / OPEN
DRAIN OUTPUT
Digital Input Pin. Used to determine autonomous−or slave mode.
Digital Input Pin. Used to determine autonomous−locked or autono-
mous−not locked mode.
Image of VINA input when VINA is within the operating range.
Used to select USB On−The−Go mode on channel 1
VINB valid indicator. This pin is used to indicate VINB is valid. Can
also be used as an input to enable both VINA and VINB channels.
VINB
POWER
Channel 2 power input path. These pins must be decoupled with a
1
mF
input capacitor.
GND
GROUND
Ground. Must be connected to a ground plane.
OUT
POWER
Output power path. Connected to battery charger. These pins must
be decoupled with a 4.7
mF
input capacitor.
VINA
POWER
Channel 1 power input path. These pins must be decoupled with a
1
mF
input capacitor.
Name
Type
Description
Pin Out
1
2
3
4
5
6
7
VINA
VINA
VINA
VINA
A
VINA
VINA
VINA
B
GND
GND
GND
VINA_S
OUT
OUT
OUT
C
MODE
GND
GND
OUT
OUT
OUT
OUT
D
CRTL
VINA_EN
/OTG
_EN
VINB_EN
/FLAG
VINB
VINB
VINB
VINB
Figure 2. Package TOP VIEW
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NCP3901
Table 2. MAXIMUM RATINGS
Rating
VINA, (Note 1)
VINA, (Note 2)
VINB, VINA_S (Note 1)
OUT (Note 1)
CTRL, MODE, VINA_EN/OTG_EN, VINB_EN/FLAG (Note 1)
Storage Temperature Range
Maximum Junction Temperature (Note 3)
Moisture Sensitivity (Note 4)
Human Body Model (HBM) ESD Rating (JEDEC standard: JESD22−A114)
Charged Device Model (CDM) ESD Rating (JEDEC standard: JESD22−A114)
Latch up Current (JEDEC standard: JESD78 class II):
V
INA
V
INB
V
OUT
V
CTRL
T
STG
T
J
MSL
ESD HBM
ESD CDM
ILU
Symbol
Value
−0.3 to +29
100
−0.3 to +21
−0.3 to +18
−0.3 to +6
−65 to +150
−40 to +TSD
Level 1
2500
2000
±100
V
V
mA
Unit
V
V
V
V
V
°C
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. With Respect to GND. According to JEDEC standard JESD22−A108.
2. With Respect to GND. According to standard IEC61000−4−5 1.2/50
ms.
3. A thermal shutdown protection avoids irreversible damage on the device due to power dissipation.
4. Moisture Sensitivity Level (MSL): 1 per IPC/JEDEC standard: J−STD−020.
Table 3. OPERATING CONDITION
Symbol
V
INA
V
INB
V
CTRL
,V
MODE
,
V
INA_EN/OTG_EN
,
V
INB_EN/FLAG
I
OUT
V
OUT
Parameter
Operational Power Supply on VINA
Operational Power Supply on VINB
Operational Supply
Conditions
Min
0
0
0
Typ
Max
28
20
5.5
Unit
V
V
V
Operational Output Current
Operational Supply on OUT
OTG mode,
VINA = VINB = 0 V
Charging mode
0
0
0
1
4.7
(Notes 3 and 5)
−40
60
25
3
5.5
17.3
A
V
V
mF
mF
°C/W
°C
C
IN
C
OUT
R
JA
T
J
Input Capacitor
Output Capacitor
Thermal Resistance Junction to Air
Junction Temperature Range
+125
5. The R
qJA
is dependent on the PCB heat dissipation. Board used to drive this data was a 2s2p JEDEC PCB standard.
Table 4. ELECTRICAL CHARACTERISTICS
Min & Max Limits apply for T
A
between −40°C to +85°C and T
J
up to + 125°C for V
IN
between V
UVLO
to V
OVLO
(Unless otherwise noted) Typical values are referenced to T
A
= + 25°C and V
IN
= 5 V (Unless otherwise noted).
Symbol
CORE
V
UVLO
Under Voltage Lockout ap-
plied to VINA, VINB or OUT
Over Voltage Lockout Re-
ferred to VINA or VINB
Stand by current
Quiescent Current
Rising
Falling
Rising
Falling
Measured on VOUT, VINA and VINB < UVLO,
OTG mode off
VINB > UVLO
VINA and VINB > UVLO (including FLAG pull down)
V
INTPUP
V
CTRLH
Internal pull up
CTRL High− input voltage
Measured on FLAG pin or MODE pin
1.6
2.2
1.8
−
2.45
−
−
17
16.4
20
100
200
2
5.5
V
V
3.0
−
V
V
V
V
mA
Parameter
Conditions
Min
Typ
Max
Unit
V
OVLO
I
OFF
I
ON
6. Guaranteed by design and characterization.
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NCP3901
Table 4. ELECTRICAL CHARACTERISTICS
Min & Max Limits apply for T
A
between −40°C to +85°C and T
J
up to + 125°C for V
IN
between V
UVLO
to V
OVLO
(Unless otherwise noted) Typical values are referenced to T
A
= + 25°C and V
IN
= 5 V (Unless otherwise noted).
Symbol
CORE
V
IH
V
IL
V
FLGL
R
FLGPUP
R
MODEPUP
R
PULDN
R
DIS
POWER
R
DSONA
R
DSONB
T
RIN
T
ROUT
I
RHMX
On resistance input VINA
On resistance input VINB
Soft Start on both channel
Soft Start on both channel
Inrush current
V
INA
> 4 V
V
INB
> 4 V
From 10% to 90% of VINA or VINB, CLOAD =
4.7
mF,
RLOAD = 500
W.
VOUT = 5V. From 10% to 90% of VINA or VINB,
CLOAD = 4.7
mF,
RLOAD = 500
W.
Supply on VINA = 5 V or 10 V or VINB = 5 V or 10 V
or VOUT = 5 V CLOAD = 4.7
mF,
RLOAD = 500
W.
(Note 6)
Total charge on C
OUT
during T
ON
time (Note 6)
Supply on VINA or VINB or VOUT CLOAD = 4.7
mF,
RLOAD = 500
W.
(Note 6)
T
ON
V
OUTMAX
Turn−on time
VOUT maximum voltage
Slave Mode, from V
INA_EN
= 1 to V
OUT
= 90% of
V
INA
or V
INB_EN
= 1 to V
OUT
= 90% of V
INB
.
VINA from 0 V to 28 V in 3 V/ms and COUT = 4.7
mF
VINB from 0 V to 20 V in 3 V/ms and COUT = 4.7
mF
100 V surge holdoff to support IEC 61000−4−5 on
VINA. (Note 6)
CONTROL and TIMING
T
DEBINA
T
DEBINB
T
CRTL
T
OTG1
T
OTG2
T
BBM
Break before make time
Debounce time for V
INA
valid
Debounce time for V
INB
valid
CRTL pin deglitcher
OTG wait time
Autonomous Mode, VINB valid, From VINA_EN/
OTG_EN = 1 to VINA valid (excluding soft start)
Autonomous Mode, VINB not valid, From VINA_EN/
OTG_EN = 1 to VINA valid (excluding soft start)
Autonomous Mode, From VINA valid to VINB valid or
from VINB valid to VINA valid
From V
UVLO
< V
INA
< V
OVLO
to V
INA
enable
(excluding soft start)
From V
UVLO
< V
INB
< V
OVLO
to V
INB
enable
(excluding soft start)
15
1
100
10
1
30
ms
ms
ms
ms
ms
ms
50
50
80
80
800
800
800
mW
mW
ms
ms
mA
MODE, VINA_EN/OTG_EN, VINB_EN/FLAG, CTRL High−level input voltage
MODE, VINA_EN/OTG_EN, CRTL, VINB_EN/FLAG, CTRL Low−level input voltage
VINB_EN/FLAG Low−level output voltage
VINB_EN/FLAG pull up resistance
MODE pin pull up resistance
VINA_EN/OTG_EN, CRTL pins pull down resistance
Output Discharge Resistance
During Break before make transition, measured on
OUT pin
1.2
0
0
50
100
500
500
5.5
0.4
0.4
V
V
V
kW
kW
kW
W
Parameter
Conditions
Min
Typ
Max
Unit
50
1
800
17.3
mC
A
ms
V
INPUT SENSE PIN
V
INSDRP
V
INSNSMX
Voltage Drop VINA – VINA_S
Max Voltage on VINA_S volt-
age sense
20 mA sink on V
INA_S
(Note 6)
200
20
mV
V
THERMAL SHUTDOWN
T
SD
Thermal Shutdown
Temperature Rising
Temperature Falling
6. Guaranteed by design and characterization.
150
135
°C
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NCP3901
Functional Description
VINA
VINA
VINA
VINA
VINA
VINA
VINA
ESD
P ROTE CTIO N
I EC61 000−4−
5
1. 2/50u s −10 /700u s
>1 00V
CHANNEL 1 BACK
TO BACK MOSFETS
OUT
OUT
OUT
OUT
OUT
OUTPUT
DICHARGE
OUT
OUT
VOVLO
IN 1 PROTECTED SENSE
OUT
VUVLO
GND
GND
GND
GND
GND
INTERNAL POWER
SUPPLY /
REFERENCE
VOLTAGE
1. 8V
V INA_S
OTG_EN / VINA _EN
CTRL
LOGIC CONTROL
MODE
LDO
VOVLO
E SD
P RO TECTI ON
1.8V
DRIVERS
VUVLO
FLAG / VINB _EN
FLAG
VINB
VINB
VINB
VINB
CHANNEL 2 BACK
TO BACK MOSFETS
NCP 3901
Figure 3. Block Diagram
Overview
The NCP3901 is a 2 to 1 flexible power source selector
with arbitration logic. A primary power path (VINA) and
secondary power path (VINB) are switched to a single pin
(OUT) that provides power to a system (battery charger
input).The two inputs (VINA and VINB) are Over Voltage
protected. The Over Voltage Threshold is set in such a way
that, considering pass MOSFET turn off time, the absolute
highest voltage at the OUT pin with a 3 V/ms rising input
voltage will be 20 V.
In addition, VINA is connected to an active clamp that
protects all downstream circuitry up to a high voltage surge
of 100 Vas defined by the IEC61000−4−5 1.2/50
ms
and
10/700
ms
standard. The IC is protected against reverse
voltage applied to the OUT pin on both inputs by use of back
to back power MOSFETs.
When a valid voltage is applied to the OUT pin, a digital
input VINA_EN/OTG_EN pin will allow this voltage to
pass through the power channel 1 from OUT to VINA.
The IC contains a VINB_EN/FLAG input that informs
the controlling logic if the secondary channel is conducting
or not.The VINB_EN/FLAG pin can also be used as an input
signal in order to enable both inputs at the same time.
The IC features a VINA_S protected and current limited
output as soon as the VINA voltage is valid (operating
range).
Depending on the MODE pin level, the IC will operate in
“Autonomous” or “Slave” mode.
•
If MODE pin is high the part operates in Slave Mode
•
If MODE pin is low the part operates in Autonomous
Mode
In Autonomous mode, the CTRL pin will prevent, if
pulled high, the part from switching from one input to the
other one. MODE digital pin, if pulled high, can also be used
to do this.
Finally, a thermal protection will stop the IC when
exceeding the TSD threshold. The IC function will be
enabled automatically when the part cools down.
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