PI6C184
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
Precision 1-13 Clock Buffer
Description
The PI6C184 is a high-speed low-noise 1-13 non-inverting
buffer designed for SDRAM clock buffer applications.
This buffer is intended to be used with the PI6C104 clock generator
for Intel Architecture for both desktop and mobile systems.
At power-up, all SDRAM outputs are enabled and active. The I
2
C
Serial control may be used to individually activate/deactivate any
of the 13 output drivers.
Note:
Purchase of I
2
C components from Pericom conveys a license to
use them in an I
2
C system as defined by Philips®.
Features
•
High-speed, low-noise, non-inverting, 1-13 buffer
•
Supports up to four SDRAM DIMMs
•
Low skew (< 250ps) between any two output clocks
•
I
2
C Serial Configuration interface
•
Multiple V
DD
, V
SS
pins for noise reduction
•
3.3V power supply voltage
•
Separate Hi-Z pin for testing
•
Packaging (Pb-free & Green available):
- 28-pin SSOP (H)
Block Diagram
Pin Configuration
SDRAM0
V
DD
SDRAM1
BUF_IN
SDRAM2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
DD
S
DRAM
11
S
DRAM
10
V
SS
V
DD
S
DRAM
9
S
DRAM
8
V
SS
V
DD
S
DRAM
7
S
DRAM
6
V
SS
V
SS
S
CLK
S
DRAM
0
S
DRAM
1
V
SS
V
DD
S
DRAM
2
SDRAM3
S
DRAM
3
V
SS
BUF_IN
SDRAM12
S
DRAM
4
S
DRAM
5
S
DRAM
12
SDATA
SCLK
I2C
I/O
V
DD
S
DATA
1
PS8320D
10/14/04
PI6C184
Precision 1-13 Clock Buffer
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
Pin Description
Pin
2 , 3 , 6 , 7 , 1 0 , 11 , 1 8 , 1 9
26,27,12
22,23
9
14
15
1,5,13,20,24,28
4,8,16,17,21,25
S y mbo l
S DRAM [0 . 7 ]
S DRAM [1 0 . 1 2 ]
S DRAM [8 . 9 ]
BUF _ IN
S DATA
S C LK
V
DD
V
SS
Ty pe
0
0
0
1
I /O
I /O
P o wer
Gro und
Qua ntit-
y
8
3
2
1
1
1
6
6
D e s criptio n
S DRAM Byte 0 clo ck o utp ut
S DRAM Byte 1 clo ck o utp ut
S DRAM Byte 2 clo ck o utp ut
Inp ut fo r 1 - 1 3 - b uffer
Data p in fo r I
2
C circuitry. Has a
1 0 0 k Internal p ull- up resisto r
C lo ck p in fo r I
2
C circuitry. Has a 1 0 0 k Internal p ull- up
resisto r
3 . 3 V p o wer sup p ly fo r S DRAM b uffer
Gro und fo r S DRAM Buffers
Serial Configuration Map
Byte0: SDRAM Active/Inactive Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
19
18
11
10
7
6
3
2
De s cription
SDRAM7 (Active/Inactive)
SDRAM6 (Active/Inactive)
SDRAM5 (Active/Inactive)
SDRAM4 (Active/Inactive)
SDRAM3 (Active/Inactive)
SDRAM2 (Active/Inactive)
SDRAM1 (Active/Inactive)
SDRAM0 (Active/Inactive)
I
2
C Address Assignment
A6
1
A5
1
A4
0
A3
1
A2
0
A1
0
A0
1
R/W
0
Note:
Inactive means outputs are held LOW and are
disabled from switching
2
PS8320D
10/14/04
321098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
321098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6C184
Precision 1-13 Clock Buffer
2-Wire I
2
C Control
The I
2
C interface permits individual enable/disable of each clock
output and test mode enable.
The PI6C184 is a slave receiver device. It can not be read back. Sub
addressing is not supported. All preceding bytes must be sent in
order to change one of the control bytes.
Every bite put on the SDATA line must be 8-bits long (MSB first),
followed by an acknowledge bit generated by the receiving device.
During normal data transfers SDATA changes only when SCLK is
LOW. Exceptions: A HIGH-to-LOW transition on SDATA while
SCLK is HIGH indicates a “start” condition. A LOW-to-HIGH
transition on SDATA while SCLK is HIGH is a “stop” condition
and indicates the end of a data transfer cycle.
Each data transfer is initiated with a start condition and ended with
Byte1: SDRAM Active/Inactive Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
12
27
26
Pin #
De s cription
NC (Initialize to 0)
NC (Initialize to 0)
NC (Initialize to 0)
NC (Initialize to 0)
NC (Initialize to 0)
SDRAM12 (Active/Inactive)
SDRAM11(Active/Inactive)
SDRAM10 (Active/Inactive)
a stop condition. The first byte after a start condition is always a
7-bit address byte followed by a read/write bit. (HIGH = read from
addressed device, LOW= write to addressed device). If the device’s
own address is detected, PI6C184 generates an acknowledge by
pulling SDATA line LOW during ninth clock pulse, then accepts
the following data bytes until another start or stop condition is
detected.
Following acknowledgement of the address byte (D2), two more
bytes must be sent:
1. “Command Code” byte, and
2. “Byte Count” byte.
Although the data bits on these two bytes are “don’t care,” they
must be sent and acknowledged.
Byte2: Optional Register for Possible Future
Requirements (1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
23
22
-
-
-
-
-
-
De s cription
SDRAM9 (Active/Inactive)
SDRAM8 (Active/Inactive)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ............................................... –65°C to +150°C
Ambient Temperature with Power Applied ................. –0°C to +70°C
3.3V Supply Voltage to Ground Potential .................. –0.5V to +4.6V
DC Input Voltage ....................................................... –0.5V to +4.6V
Note:
Stresses greater than those listed under MAXIMUM RAT-
INGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at
these or any other conditions above those indicated in the
operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
Supply Current
(V
DD
= +3.465V, C
LOAD
= Max.)
S ymbo l
I
DD
I
DD
I
DD
Pa ra me te r
S up p ly C urrent
S up p ly C urrent
S up p ly C urrent
Te s t Co nditio n
BUF _IN = 0 MHz
BUF _IN = 6 6 . 6 6 MHz
BUF _IN = 10 0 . 0 MHz
M in.
Typ.
M ax.
3
230
360
mA
Units
3
PS8320D
10/14/04
PI6C184
Precision 1-13 Clock Buffer
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
DC Operating Specifications
(V
DD
= +3.3V ±5%, T
A
= 0°C - 70°C)
Symbol
Input Voltage
V
IH
V
IL
I
IL
V
OH
V
OL
C
OUT
C
IN
L
PIN
T
A
Input high voltage
Input low voltage
Input leakage current
Output high voltage
Output low voltage
Output pin capacitance
Input pin capacitance
Pin Inductance
Ambient Temperature
No Airflow
0
0 < V
IN
< V
DD
I
OH
= - 1mA
I
OL
= 1mA
V
DD
2.0
V
SS
–0.3
–5
2.4
0.4
6
5
7
70
V
DD
+0.3
0.8
+5
V
mA
Parame te r
Te s t Condition
M in.
M a x.
Units
V
DD
[0- 9] = 3.3V ±5%
V
pF
nH
°C
SDRAM Clock Buffer Operating Specification
Symbol
I
OHMIN
I
OHMAX
I
OLMIN
I
OLMAX
t
RH
SDRAM
t
TH
SDRAM
Parame te r
Pull- up current
Pull- up current
Pull- down current
Pull- down current
Output rise edge rate SDRAM only
Output fall edge rate SDRAM only
Te s t Conditions
V
OUT
= 2.0V
V
OUT
= 3.135V
V
OUT
= 1.0V
V
OUT
= 0.4V
3.3V ±5% @ 04V- 2.4V
3.3V ±5% @ 2.4V- 0.4V
1.5
1.5
54
53
4
4
V/ns
M in.
–54
–46
mA
Typ.
M ax.
Units
AC Timing
66 MHz
Min. Max.
T
DSKP
SDRAM CLK period
15.0
15.5
T
SDKH
SDRAM CLK high time
5.6
T
SDKL
SDRAM CLK low time
5.3
T
SDRISE
SDRAM CLK rise time
1.5
4.0
T
SDFALL
SDRAM CLK fall time
1.5
4.0
t
PLH
SDRAM Buffer LH prop delay
1.0
5.5
t
PHL
SDRAM Buffer HL prop delay
1.0
5.5
DutyCycle Measured at 1.5V
45
55
tSDSKW
SDRAM Output to Output Skew
250
Symbol
Parameter
100 MHz
Min.
Max.
10.0
10.5
3.3
3.1
1.5
4.0
1.5
4.0
1.0
5.0
1.0
5.0
45
55
250
Units
ns
ns
ns
V/ns
V/ns
ns
ns
%
ps
4
PS8320D
10/14/04
321098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
321098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
Output
Buffer
Test
Point
Test Load
PI6C184
Precision 1-13 Clock Buffer
tSDKP
tSDKH
3.3V
Clocking
Interface
(TTL)
2.4
1.5
0.4
tSDKL
t
SDRISE
t
SDFALL
Input
Waveform
t
plh
Output
Waveform
1.5V
1.5V
t
phl
1.5V
1.5V
Figure 1. Clock Waveforms
Minimum and Maximum Expected Capacitive Loads
Clock
SDRAM
M in. Load
20
M ax. Load
30
Units
pF
Note s
SDRAM DIMM Specification
Notes:
1. Maximum rise/fall times are guaranteed at maximum specified load.
2. Minimum rise/fall times are guaranteed at minimum specified load.
3. Rise/fall times are specified with pure capacitive load as shown.
Testing is done with an additional 500Ω resistor in parallel.
Design Guidelines to Reduce EMI
1. Place series resistors and CI capacitors as close as possible to the respective clock pins. Typical value
for CI is 10pF. Series resistor value can be increased to reduce EMI provided that the rise and fall time
are still within the specified values.
2. Minimize the number of “vias” of the clock traces.
3. Route clock traces over a continuous ground plane or over a continuous power plane. Avoid routing
clock traces from plane to plane (refer to rule #2).
4. Position clock signals away from signals that go to any cables or any external connectors.
5
PS8320D
10/14/04
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