21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6C184-02
Precision 1-13 Clock Buffer
Features
•
High speed, low noise non-inverting 1-13 buffer
•
Supports up to four SDRAM DIMMs
•
Low skew (<250ps) between any two output clocks
•
I
2
C Serial Configuration interface
•
Multiple V
DD
, V
SS
pins for noise reduction
•
3.3V power supply voltage
•
28-pin SSOP and SOIC packages (H, S)
Description
The PI6C184-02 is a high-speed low-noise 1-13 non-inverting
buffer designed for SDRAM clock buffer applications.
This buffer is intended to be used with the PI6C104 clock generator
for Intel Architecture for both desktop and mobile systems.
At power up all SDRAM output are enabled and active. The
I
2
C Serial control may be used to individually activate/deactivate
any of the 13 output drivers.
Note:
Purchase of I
2
C components from Pericom conveys a license to
use them in an I
2
C system as defined by Philips.
Block Diagram
SDRAM0
Pin Configuration
SDRAM1
BUF_IN
SDRAM2
SDRAM3
SDRAM12
SDATA
SCLOCK
I2C
I/O
V
DD
SDRAM0
SDRAM1
V
SS
V
DD
SDRAM2
SDRAM3
V
SS
BUF_IN
SDRAM4
SDRAM5
SDRAM12
V
DD
SDATA
1
2
3
4
5
6
28-Pin
H, S
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
DD
SDRAM11
SDRAM10
V
SS
V
DD
SDRAM9
SDRAM8
V
SS
V
DD
SDRAM7
SDRAM6
V
SS
V
SS
SCLK
1
PS8319
05/03/00
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PI6C184-02
Precision 1-13 Clock Buffer
Pin Description
Pin
2,3,6,7,10,11,
18,19,22,23,26,27
12
9
14
154
1,5,13,20,24,28
4,8,16,17,21,25
Symbol
SDRAM [0.5]
SDRAM [6.11]
SDRAM [12]
BUF_IN
SDATA
SCLOCK
V
DD
V
SS
Type
0
0
0
1
I/O
I/O
Power
Ground
Quantity
6
6
1
1
1
1
6
6
De s cription
SDRAM Byte 0 clock output
SDRAM Byte 1 clock output
SDRAM Byte 2 clock output
Input for 1- 13- buffer
Data pin for I
2
C circuitry. Has a 100k
Internal pull- up resistor
Clock pin for I
2
C circuitry. Has a
100k Internal pull- up resistor
3.3V power supply for SDRAM buffer
Ground for SDRAM Buffers
PI6C184-02
I
2
C Address Assignment
A6
1
A5
1
A4
0
A3
1
A2
0
A1
0
A0
1
R/W
0
PI6C184 Serial Configuration Map
Byte0: SDRAM Active/Inactive Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Note:
Pin #
11
10
~
~
7
6
3
2
De s cription
SDRAM5 (Active/Inactive)
SDRAM4(Active/Inactive)
Reserved
Reserved
SDRAM3 (Active/Inactive)
SDRAM2 (Active/Inactive)
SDRAM1 (Active/Inactive)
SDRAM0 (Active/Inactive)
Inactive means outputs are held LOW and
are disabled from switching
2
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21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6C184-02
Precision 1-13 Clock Buffer
2-Wire I
2
C Control
The I
2
C interface permits individual enable/disable of each
clock output and test mode enable.
The PI6C184-02 is a slave receiver device. It can not be read
back. Sub addressing is not supported. All preceding bytes
must be sent in order to change one of the control bytes.
Every bite put on the SDATA line must be 8-bits long (MSB
first), followed by an acknowledge bit generated by the
receiving device.
During normal data transfers Sdata changes only when SCLK
is LOW. Exceptions: A HIGH to LOW transition on SDATA
while SCLK is HIGH indicates a “start” condition. A LOW to
HIGH transition on SDATA while SCLK is HIGH is a “stop”
condition and indicates the end of a data transfer cycle.
Each data transfer is initiated with a start condition and ended
with a stop condition. The first byte after a start condition is
always a 7-bit address byte followed by a read/write bit. (HIGH
= read from addressed device, LOW = write to addressed
device). If the device’s own address is detected, PI6C184-02
generates an acknowledge by pulling SDATA line LOW during
ninth clock pulse, then accepts the following data bytes until
another start or stop condition is detected.
Following acknowledgement of the address byte (D2), two more
bytes must be sent:
1. “Command Code” byte, and
2. “Byte Count” byte.
Although the data bits on these two bytes are “don’t care,” they
must be sent and acknowledged.
Byte2: Optional Register for Possible Future
Requirements (1 = enable, 0 = disable)
1
2
3
4
5
6
7
8
9
Byte1: SDRAM Active/Inactive Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
27
26
23
22
N/A
N/A
19
18
De s cription
SDRAM11 (Active/Inactive)
SDRAM10 (Active/Inactive)
SDRAM9 (Active/Inactive)
SDRAM8 (Active/Inactive)
(Reserved)
(Reserved)
SDRAM7 (Active/Inactive)
SDRAM6 (Active/Inactive)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
N/A
12
N/A
N/A
N/A
N/A
N/A
N/A
(Reserved)
De s cription
SDRAM12 (Active/Inactive)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
10
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ................................................ –65°C to +150°C
Ambient Temperature with Power Applied ............. –0°C to +70°C
3.3V Supply Voltage to Ground Potential ............... –0.5V to +4.6V
DC Input Voltage ..................................................... –0.5V to +4.6V
Note:
Stresses greater than those listed under MAXIMUM
RATINGS may cause permanent damage to the device. This
is a stress rating only and functional operation of the device
at these or any other conditions above those indicated in the
operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for ex-
tended periods may affect reliability.
11
12
13
Supply Current (V
DD
= +3.465V, Cload = max)
Symbol
I
DD
I
DD
I
DD
Parame te r
Supply Current
Supply Current
Supply Current
Te s t Condition
BUF_IN = 0 MHz
BUF_IN = 66.66 MHz
BUF_IN = 100.0 MHz
M in.
Typ.
M ax
3
230
360
mA
Units
14
15
3
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PI6C184-02
Precision 1-13 Clock Buffer
DC Operating Specifications (V
DD
= +3.3V ±5%, T
A
= 0°C - 70°C)
Symbol
Parame te r
Te s t Condition
M in.
M ax.
Units
Input Voltage , V
DDCORE
[0-1] = 3.3V± 5%
V
IH
V
IL
I
IL
V
OH
V
OL
C
IN
C
OUT
L
PIN
T
A
Input High Voltage
Input Low Voltage
Input Leakage Current
0 < V
IN
< V
DD
I
OH
= 1mA
I
OL
= 1mA
V
DD
2.0
V
SS
0.3
-5
V
DDCORE
+0.3
0.8
+5
V
V
DD
= 3.3V ± 5%
Output High Voltage
Output Low Voltage
Input Pin Capacitance
Output pins Capacitance
Pin Inductance
Ambient Temperature
No Airflow
0
2.4
0.4
5
6
7
70
V
pF
nH
ºC
SDRAM Clock Buffer Operating Specification
Symbol
I
OHMIN
I
OHMAX
I
OLMIN
I
OLMAX
t
RH
SDRAM
t
FH
SDRAM
Parame te r
Pull- up current
Pull- up current
Pull- down current
Pull- down current
O utput rise edge rate
SDRAM only
O utput fall edge rate
SDRAM only
Condition
V
OUT
= 2.0V
V
OUT
= 3.135V
V
OUT
= 1.0V
V
OUT
= 0.4V
3.3V ±5%
@04V- 2.4V
3.3V ±5%
@2.4V- 0.4V
1.5
1.5
54
53
4
4
V/ns
M in. Typ.
54
46
mA
M ax.
Units
AC Timing
Symbol
tSDKP
tSDKH
tSDKL
tSDRISE
tSDFALL
tpLH
tpHL
tpZL,tpZH
tpLZ,tpHZ
Duty Cycle
tSDSKW
Parame te r
SDRAM CLK period
SDRAM CLK high time
SDRAM CLK low time
SDRAM CLK rise time
SDRAM CLK fall time
SDRAM Buffer LH prop delay
SDRAM Buffer HL prop delay
SDRAM Buffer Enable delay
SDRAM Buffer Disable delay
Measured at 1.5V
SDRAM Output to
Output Skew
66 M Hz
M in.
15.0
5.6
5.3
1.5
1.5
1.0
1.0
1.0
1.0
45
4.0
4.0
5.0
5.0
8.0
8.0
55
250
M ax.
15.5
100 M Hz
M in.
10.0
3.3
3.1
1.5
1.5
1.0
1.0
1.0
1.0
45
4.0
4.0
5.0
5.0
8.0
8.0
55
250
%
ps
ns
V/ns
M ax.
10.5
ns
Units
4
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21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
Output
Buffer
Test
Point
PI6C184-02
Precision 1-13 Clock Buffer
1
2
Test Load
tSDKP
tSDKH
3
4
tSDKL
3.3V
Clocking
Interface
(TTL)
2.4
1.5
0.4
5
6
t
SDRISE
t
SDFALL
Input
Waveform
t
plh
Output
Waveform
1.5V
1.5V
t
phl
7
8
9
1.5V
1.5V
Figure 1. Clock Waveforms
Minimum and Maximum Expected Capacitive Loads
Clock
SDRAM
M in Load M ax Load
20
30
Units
pF
Note s
SDRAM DIMM
Specification
10
11
Notes:
1. Maximum rise/fall times are guaranteed at maximum specified load.
2. Minimum rise/fall times are guaranteed at minimum specified load.
3. Rise/fall times are specified with pure capacitive load as shown.
Testing is done with an additional 500Ω resistor in parallel.
12
13
Design Guidelines to Reduce EMI
1. Place series resistors and CI capacitors as close as possible to the respective clock pins. Typical value
for CI is 10 pF. Series resistor value can be increased to reduce EMI provided that the rise and fall
time are still within the specified values.
2. Minimize the number of “vias” of the clock traces.
3. Route clock traces over a continuous ground plane or over a continuous power plane. Avoid routing
clock traces from plane to plane (refer to rule #2).
4. Position clock signals away from signals that go to any cables or any external connectors.
14
15
5
PS8319
05/03/00
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