AN078
Getting Started
1. Introduction
This application note will help developers quickly implement proof-of-concept designs using the
KX116, KX126,
and
KX127
tri-axis accelerometers with built-in pedometer Please refer to the
corresponding Product Specifications document for additional implementation guidelines. Kionix
strives to ensure that our accelerometers will meet design expectations by default, but it is not
possible to provide default setting to work in every environment. Depending on the intended
application, it is very likely that some customization will be required to optimize performance. The
information provided here will help the developer get the most out of these tri-axis accelerometers.
Note: Pedometer functionality and details are not covered in this document. Please refer to
AN073
Getting Started with Pedometer
for more information.
2. Circuit Schematic
This section shows recommended wiring for this accelerometer, based on proven operation of the
part. Specific applications may require modifications from these recommendations. Please refer to
the corresponding Product Specifications document for all pin descriptions.
Figure 1:
KX116, KX126 Application Schematic
36 Thornwood Dr.
—
Ithaca, NY 14850 USA
Tel: 607-257-1080
—
Fax: 607-257-1146
www.kionix.com
—
info@kionix.com
© Kionix 2018 All Rights Reserved
28 February 2018
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AN078
Figure 2:
KX127 Application Schematic
© Kionix 2018 All Rights Reserved
28 February 2018
Page 2 of 24
AN078
3. Quick Start Implementations
Here we present several basic ways to initialize the part. These can vary based on desired operation,
but generally the initial operations a developer wants to do are: 1) read back acceleration data
asynchronously, 2) read back acceleration data when next data is ready via interrupt (synchronous
data reading), 3) use of the sample buffer, 4) use the Wake-Up function, 5) activate the tilt position
function, 6) activate the tap/double-tap function, and 7) activate the free-fall function. These cursory
solutions are provided as a means for configuring the part to a known operational state. Note that
these conditions just provide a starting point, and the values may vary as developers refine their
application requirements.
4. Asynchronous Read Back Acceleration Data (Setting G-Range and ODR)
-
Write 0x40 to Control Register 1 (CNTL1) to set the accelerometer in stand-by mode, to set
the performance mode to High Resolution (full power) and G-range to ±2g.
Register Name
CNTL1
-
-
Register Name
ODCNTL
-
Address
0x1F
Value
0x02
Address
0x1A
Value
0x40
Write 0x02 to Data Control Register (ODCNTL) to set the Output Data Rate (ODR) of the
accelerometer to 50 Hz.
This step is optional as this is also a default setting.
Write 0xC0 to Control Register 1 (CNTL1) to set the accelerometer into operating mode (PC1
= 1)
Register Name
CNTL1
Address
0x1A
Value
0xC0
-
Acceleration data can now be read from the XOUT_L, XOUT_H, YOUT_L, YOUT_H,
ZOUT_L, and ZOUT_H registers in 2’s complement format.
© Kionix 2018 All Rights Reserved
28 February 2018
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AN078
5. Synchronous Hardware Interrupt Read Back Acceleration Data (Setting G-
Range and ODR)
-
Write 0x60 to Control Register 1 (CNTL1) to set the accelerometer in stand-by mode, to set
the performance mode of the sensor to High Resolution (full power), G-range to ±2g, and
enable the availability of new data as an interrupt.
Register Name
CNTL1
-
Address
0x1A
Value
0x60
Write 0x38 to Interrupt Control Register (INC1) to enable physical interrupt pin INT1, to set
the polarity of the physical interrupt to active high and to transmit interrupt pulses with a
period of 0.03 ms to 0.05 ms in pin (5).
Register Name
INC1
Address
0x20
Value
0x38
-
Write 0x10 to Interrupt Control Register 4 (INC4) to set the Data Ready interrupt to be
reported on physical interrupt pin INT1.
Register Name
INC4
Address
0x23
Value
0x10
-
-
Write 0x02 to Data Control Register (ODCNTL) to set the Output Data Rate (ODR) of the
accelerometer to 50 Hz.
This step is optional as this is also a default setting.
Register Name
ODCNTL
Address
0x1F
Value
0x02
-
Write 0xE0 to Control Register 1 (CNTL1) to set the accelerometer into operating mode (PC1
= 1)
Register Name
CNTL1
Address
0x1A
Value
0xE0
-
Acceleration data can now be read from the XOUT_L, XOUT_H, YOUT_L, YOUT_H,
ZOUT_L, and ZOUT_H registers in 2’s complement format.
© Kionix 2018 All Rights Reserved
28 February 2018
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AN078
6. Sample Buffer Operation
6.1.
Sample Buffer-Full Interrupt via Physical Hardware Interrupt
-
Write 0x00 to Control Register 1 (CNTL1) to set the accelerometer in stand-by mode, to
set the performance mode of the accelerometer to Low Current mode, and G-range to
±2g.
Register Name
CNTL1
-
Address
0x1A
Value
0x00
Write 0x38 to Interrupt Control Register (INC1) to enable physical interrupt pin INT1, to set
the polarity of the physical interrupt to active high and to transmit interrupt pulses with a
period of 0.03 ms to 0.05 ms in pin (5).
Register Name
INC1
Address
0x20
Value
0x38
-
Write 0x40 to Interrupt Control Register 4 (INC4) to set the Buffer Full interrupt to be
reported on physical interrupt pin INT1.
Register Name
INC4
Address
0x23
Value
0x40
-
Write 0x02 to Data Control Register (ODCNTL) to set the Output Data Rate (ODR) of the
accelerometer to 50 Hz.
This step is optional as this is also a default setting.
Register Name
ODCNTL
-
Address
0x1F
Value
0x02
Write 0xA0 to Buffer Control Register 2 (BUF_CNTL2) to activate the sample buffer, to set
the resolution of the acceleration data samples collected to 8 bits, to enable report of the
interrupt status in INS2, and set the operating mode of the sample buffer to FIFO.
Register Name
BUF_CNTL2
Address
0x5B
Value
0xA0
-
Write 0x80 to Control Register 1 (CNTL1) to set the accelerometer into operating mode
(PC1 = 1)
Register Name
CNTL1
Address
0x1A
Value
0x80
-
Once Buffer-Full Interrupt is issued on INT1 pin, acceleration data can then be read from
the Buffer Read (BUF_READ) register at address 0x3F in 2’s complement format. Since
the resolution of the samples data was set to 8-bit, only the most significant 8 bits of each
sample will be stored in the buffer, and recorded in the following order: X_HIGH, Y_HIGH,
Z_HIGH with the oldest data point read first as it is a FIFO buffer. The full buffer contains
2049 X, Y, Z elements, which corresponds to 683 unique acceleration data samples.
(Note: With BRES=0, in BUF_CNTL2 register, is is possible to collect 342 16-bit samples).
© Kionix 2018 All Rights Reserved
28 February 2018
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