598BBB000118DG datasheet, PDF - EEWORLD Datasheet

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598BBB000118DG: DescriptionOSC XO 156.2500MHZ LVDS SMD; CategoryPassive components; File Size550KB，27 Pages; ManufacturerSilicon Laboratories Inc

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598BBB000118DG Overview

OSC XO 156.2500MHZ LVDS SMD

598BBB000118DG Parametric

Parameter Name	Attribute value
type	XO (Standard)
frequency	156.25MHz
Function	enable/disable (programmable)
output	LVDS
Voltage - Power	2.97 V ~ 3.63 V
frequency stability	±25ppm
Absolute pulling range (APR)	-
Operating temperature	-40°C ~ 85°C
Current - Power (maximum)	110mA
grade	-
Installation type	surface mount
Package/casing	8-SMD, no leads
size/dimensions	0.276" long x 0.197" wide (7.00mm x 5.00mm)

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Si 5 9 8 / S i 5 9 9

10–810 M H

C P

ROGRAMMABLE

XO/VCXO

Features



C programmable output

frequencies from 10 to 810 MHz

0.5 ps RMS phase jitter

Superior power supply rejection:

0.3–0.4 ps additive jitter

Available LVPECL, CMOS, LVDS,

and CML outputs

1.8, 2.5, or 3.3 V supply

Pin- and register-compatible with

Si570/571



Programmable with 28 parts per

trillion frequency resolution

Integrated crystal provides stability

and low phase noise

Frequency changes up to

±3500 ppm are glitchless

–40 to 85 °C operation

Industry-standard 5x7 mm package

Si5602

Applications



Ordering Information:



SONET / SDH / xDSL

Ethernet / Fibre Channel

3G SDI / HD SDI

Multi-rate PLLs

Multi-rate reference clocks

Frequency margining

Digital PLLs

CPU / FPGA FIFO control

Adaptive synchronization

Agile RF local oscillators

See page 21.

Pin Assignments:

See page 20.

(Top View)

SDA

SCL

Description

The Si598 XO/Si599 VCXO utilizes Silicon Laboratories' advanced DSPLL®

circuitry to provide a low-jitter clock at any frequency. They are user-

programmable to any output frequency from 10 to 810 MHz with 28 parts per

trillion (PPT) resolution. The device is programmed via a 2-pin I

C compatible

serial interface. The wide frequency range and ultra-fine programming resolution

make these devices ideal for applications that require in-circuit dynamic frequency

adjustments or multi-rate operation with non-integer related rates. Using an

integrated crystal, these devices provide stable low jitter frequency synthesis and

replace multiple XOs, clock generators, and DAC controlled VCXOs.

GND

CLK–

CLK+

Functional Block Diagram

Power Supply Filtering

Si598

SDA

Fixed

Frequency

Oscillator

Any Frequency

DSPLL®

10 to 810 MHz

Clock Synthesis

CLK+

CLK–

SCL

(Si599)

CLK–

CLK+

ADC

I2C Interface

GND

SDA

SCL

GND

Si599

Rev. 1.1 6/18

Si598/Si599

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