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74VCX132MTC

Description
Low Voltage Quad 2-Input NAND Gate with Schmitt Trigger Inputs and 3.6V Tolerant Inputs and Outputs
Categorylogic    logic   
File Size497KB,10 Pages
ManufacturerFairchild
Websitehttp://www.fairchildsemi.com/
Environmental Compliance
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74VCX132MTC Overview

Low Voltage Quad 2-Input NAND Gate with Schmitt Trigger Inputs and 3.6V Tolerant Inputs and Outputs

74VCX132MTC Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerFairchild
Parts packaging codeTSSOP
package instructionTSSOP, TSSOP14,.25
Contacts14
Reach Compliance Codeunknow
seriesALVC/VCX/A
JESD-30 codeR-PDSO-G14
JESD-609 codee3
length5 mm
Load capacitance (CL)30 pF
Logic integrated circuit typeNAND GATE
MaximumI(ol)0.024 A
Humidity sensitivity level1
Number of functions4
Number of entries2
Number of terminals14
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Package body materialPLASTIC/EPOXY
encapsulated codeTSSOP
Encapsulate equivalent codeTSSOP14,.25
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
method of packingRAIL
Peak Reflow Temperature (Celsius)260
power supply3.3 V
Prop。Delay @ Nom-Su3.3 ns
propagation delay (tpd)16.4 ns
Certification statusNot Qualified
Schmitt triggerYES
Maximum seat height1.2 mm
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)1.4 V
Nominal supply voltage (Vsup)1.5 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceMatte Tin (Sn)
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width4.4 mm
74VCX132 Low Voltage Quad 2-Input NAND Gate with Schmitt Trigger Inputs and 3.6V Tolerant Inputs and
Outputs
July 1999
Revised February 2005
74VCX132
Low Voltage Quad 2-Input NAND Gate
with Schmitt Trigger Inputs
and 3.6V Tolerant Inputs and Outputs
General Description
The VCX132 contains four 2-input NAND gates with
Schmitt Trigger Inputs. The pin configuration and function
are the same as the VCX00 except the inputs have hyster-
esis between the positive-going and negative-going input
thresholds. This hysteresis is useful for transforming slowly
switching input signals into sharply defined, jitter-free out-
put signals. This product should be used where noise mar-
gin greater than that of conventional gates is required.
The VCX132 is designed for low voltage (1.4V to 3.6V) V
CC
applications with I/O compatibility up to 3.6V.
This product is fabricated with an advanced CMOS tech-
nology to achieve high-speed operation while maintaining
low CMOS power dissipation.
Features
s
1.4V to 3.6V V
CC
supply operation
s
3.6V tolerant inputs and outputs
s
t
PD
3.3 ns max for 3.0V to 3.6V V
CC
s
Power-off high impedance inputs and outputs
s
Static Drive (I
OH
/I
OL
)
r
24 mA @ 3.0V V
CC
s
Uses patented Quiet Series
¥
noise/EMI reduction
circuitry
s
Latchup performance exceeds JEDEC 78 conditions
s
ESD performance:
Human body model
!
2000V
Machine model
!
250V
s
Leadless Pb-Free DQFN package
Ordering Code:
Order Number Package Number
74VCX132M
74VCX132BQX
(Note 1)
74VCX132MTC
M14A
MLP014A
MTC14
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Pb-Free 14-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC
MO-241, 2.5 x 3.0mm
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Note 1:
DQFN package available in Tape and Reel only.
Quiet Series
¥
is a trademark of Fairchild Semiconductor Corporation.
© 2005 Fairchild Semiconductor Corporation
DS500164
www.fairchildsemi.com

74VCX132MTC Related Products

74VCX132MTC 74VCX132 74VCX132BQX 74VCX132M 74VCX132_05
Description Low Voltage Quad 2-Input NAND Gate with Schmitt Trigger Inputs and 3.6V Tolerant Inputs and Outputs Low Voltage Quad 2-Input NAND Gate with Schmitt Trigger Inputs and 3.6V Tolerant Inputs and Outputs Low Voltage Quad 2-Input NAND Gate with Schmitt Trigger Inputs and 3.6V Tolerant Inputs and Outputs Low Voltage Quad 2-Input NAND Gate with Schmitt Trigger Inputs and 3.6V Tolerant Inputs and Outputs Low Voltage Quad 2-Input NAND Gate with Schmitt Trigger Inputs and 3.6V Tolerant Inputs and Outputs
Is it Rohs certified? conform to - conform to conform to -
Maker Fairchild - Fairchild Fairchild -
Parts packaging code TSSOP - QFN SOIC -
package instruction TSSOP, TSSOP14,.25 - 2.50 X 3 MM, MO-241AA, DQFN-14 SOP, SOP14,.25 -
Contacts 14 - 14 14 -
Reach Compliance Code unknow - compli unknow -
series ALVC/VCX/A - ALVC/VCX/A ALVC/VCX/A -
JESD-30 code R-PDSO-G14 - R-XQCC-N14 R-PDSO-G14 -
JESD-609 code e3 - e3 e3 -
length 5 mm - 3 mm 8.6235 mm -
Load capacitance (CL) 30 pF - 30 pF 30 pF -
Logic integrated circuit type NAND GATE - NAND GATE NAND GATE -
MaximumI(ol) 0.024 A - 0.024 A 0.024 A -
Humidity sensitivity level 1 - 1 1 -
Number of functions 4 - 4 4 -
Number of entries 2 - 2 2 -
Number of terminals 14 - 14 14 -
Maximum operating temperature 85 °C - 85 °C 85 °C -
Minimum operating temperature -40 °C - -40 °C -40 °C -
Package body material PLASTIC/EPOXY - UNSPECIFIED PLASTIC/EPOXY -
encapsulated code TSSOP - HVQCCN SOP -
Encapsulate equivalent code TSSOP14,.25 - LCC14,.1X.12,20 SOP14,.25 -
Package shape RECTANGULAR - RECTANGULAR RECTANGULAR -
Package form SMALL OUTLINE, THIN PROFILE, SHRINK PITCH - CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE SMALL OUTLINE -
method of packing RAIL - TAPE AND REEL RAIL -
Peak Reflow Temperature (Celsius) 260 - NOT SPECIFIED 260 -
power supply 3.3 V - 3.3 V 3.3 V -
Prop。Delay @ Nom-Su 3.3 ns - 3.3 ns 3.3 ns -
propagation delay (tpd) 16.4 ns - 16.4 ns 16.4 ns -
Certification status Not Qualified - Not Qualified Not Qualified -
Schmitt trigger YES - YES YES -
Maximum seat height 1.2 mm - 0.8 mm 1.753 mm -
Maximum supply voltage (Vsup) 3.6 V - 3.6 V 3.6 V -
Minimum supply voltage (Vsup) 1.4 V - 1.4 V 1.4 V -
Nominal supply voltage (Vsup) 1.5 V - 1.5 V 1.5 V -
surface mount YES - YES YES -
technology CMOS - CMOS CMOS -
Temperature level INDUSTRIAL - INDUSTRIAL INDUSTRIAL -
Terminal surface Matte Tin (Sn) - Tin (Sn) Matte Tin (Sn) -
Terminal form GULL WING - NO LEAD GULL WING -
Terminal pitch 0.65 mm - 0.5 mm 1.27 mm -
Terminal location DUAL - QUAD DUAL -
Maximum time at peak reflow temperature NOT SPECIFIED - NOT SPECIFIED NOT SPECIFIED -
width 4.4 mm - 2.5 mm 3.9 mm -
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