74HC193N,652 datasheet, PDF - EEWORLD Datasheet

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74HC193N,652: DescriptionIC 4BIT BINARY UP/DN COUNT 16DIP; Categorylogic logic; File Size179KB，30 Pages; ManufacturerNXP; Websitehttps://www.nxp.com; Environmental Compliance

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74HC193N,652 Overview

IC 4BIT BINARY UP/DN COUNT 16DIP

74HC193N,652 Parametric

Parameter Name	Attribute value
Brand Name	NXP Semiconductor
Is it Rohs certified?	conform to
Maker	NXP
Parts packaging code	DIP
package instruction	DIP, DIP16,.3
Contacts	16
Manufacturer packaging code	SOT38-4
Reach Compliance Code	compliant
Other features	TCO UP AND TCO DOWN OUTPUTS; SEPARATE UP/DOWN CLOCK
Counting direction	BIDIRECTIONAL
series	HC/UH
JESD-30 code	R-PDIP-T16
JESD-609 code	e4
length	19.025 mm
Load capacitance (CL)	50 pF
Load/preset input	YES
Logic integrated circuit type	BINARY COUNTER
Maximum Frequency@Nom-Sup	13000000 Hz
MaximumI(ol)	0.004 A
Operating mode	SYNCHRONOUS
Number of digits	4
Number of functions	1
Number of terminals	16
Maximum operating temperature	125 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	DIP
Encapsulate equivalent code	DIP16,.3
Package shape	RECTANGULAR
Package form	IN-LINE
method of packing	BULK PACK
Peak Reflow Temperature (Celsius)	260
power supply	2/6 V
propagation delay (tpd)	65 ns
Certification status	Not Qualified
Maximum seat height	4.2 mm
Maximum supply voltage (Vsup)	6 V
Minimum supply voltage (Vsup)	2 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	CMOS
Temperature level	AUTOMOTIVE
Terminal surface	NICKEL PALLADIUM GOLD
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	30
Trigger type	POSITIVE EDGE
width	7.62 mm
minfmax	13 MHz
Base Number Matches	1

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74HC193; 74HCT193

Presettable synchronous 4-bit binary up/down counter

Rev. 4 — 24 June 2013

Product data sheet

1. General description

The 74HC193; 74HCT193 is a 4-bit synchronous binary up/down counter. Separate

up/down clocks, CPU and CPD respectively, simplify operation. The outputs change state

synchronously with the LOW-to-HIGH transition of either clock input. If the CPU clock is

pulsed while CPD is held HIGH, the device will count up. If the CPD clock is pulsed while

CPU is held HIGH, the device will count down. Only one clock input can be held HIGH at

any time to guarantee predictable behaviour. The device can be cleared at any time by the

asynchronous master reset input (MR); it may also be loaded in parallel by activating the

asynchronous parallel load input (PL). The terminal count up (TCU) and terminal count

down (TCD) outputs are normally HIGH. When the circuit has reached the maximum

count state of 15, the next HIGH-to-LOW transition of CPU will cause TCU to go LOW.

TCU will stay LOW until CPU goes HIGH again, duplicating the count up clock. Likewise,

the TCD output will go LOW when the circuit is in the zero state and the CPD goes LOW.

The terminal count outputs can be used as the clock input signals to the next higher order

circuit in a multistage counter, since they duplicate the clock waveforms. Multistage

counters will not be fully synchronous, since there is a slight delay time difference added

for each stage that is added. The counter may be preset by the asynchronous parallel

load capability of the circuit. Information present on the parallel data inputs (D0 to D3) is

loaded into the counter and appears on the outputs (Q0 to Q3) regardless of the

conditions of the clock inputs when the parallel load (PL) input is LOW. A HIGH level on

the master reset (MR) input will disable the parallel load gates, override both clock inputs

and set all outputs (Q0 to Q3) LOW. If one of the clock inputs is LOW during and after a

reset or load operation, the next LOW-to-HIGH transition of that clock will be interpreted

as a legitimate signal and will be counted. Inputs include clamp diodes. This enables the

use of current limiting resistors to interface inputs to voltages in excess of V

2. Features and benefits



Input levels:



For 74HC193: CMOS level



For 74HCT193: TTL level



Synchronous reversible 4-bit binary counting



Asynchronous parallel load



Asynchronous reset



Expandable without external logic



Complies with JEDEC standard no. 7A



ESD protection:



HBM JESD22-A114F exceeds 2000 V



MM JESD22-A115-A exceeds 200 V.

74HC193N,652 Related Products

	74HC193N,652	74HCT193N,652	74HCT193PW-T	935283088118
Description	IC 4BIT BINARY UP/DN COUNT 16DIP	IC COUNTER UP/DOWN SYNC 16-DIP	IC HCT SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL BINARY COUNTER, PDSO16, Counter	HCT SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL BINARY COUNTER, PDSO16, 4.40 MM, PLASTIC, MO-153, SOT403-1, TSSOP-16
Reach Compliance Code	compliant	compliant	unknown	unknown
Other features	TCO UP AND TCO DOWN OUTPUTS; SEPARATE UP/DOWN CLOCK	TCO UP AND TCO DOWN OUTPUTS; SEPARATE UP/DOWN CLOCK	TCO UP AND TCO DOWN OUTPUTS; SEPARATE UP/DOWN CLOCK	TCO UP AND TCO DOWN OUTPUTS; SEPARATE UP/DOWN CLOCK
Counting direction	BIDIRECTIONAL	BIDIRECTIONAL	BIDIRECTIONAL	BIDIRECTIONAL
series	HC/UH	HCT	HCT	HCT
JESD-30 code	R-PDIP-T16	R-PDIP-T16	R-PDSO-G16	R-PDSO-G16
length	19.025 mm	21.6 mm	5 mm	5 mm
Load/preset input	YES	YES	YES	YES
Logic integrated circuit type	BINARY COUNTER	BINARY COUNTER	BINARY COUNTER	BINARY COUNTER
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Number of digits	4	4	4	4
Number of functions	1	1	1	1
Number of terminals	16	16	16	16
Maximum operating temperature	125 °C	125 °C	125 °C	125 °C
Minimum operating temperature	-40 °C	-40 °C	-40 °C	-40 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	DIP	DIP	TSSOP	TSSOP
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	IN-LINE	IN-LINE	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
propagation delay (tpd)	65 ns	65 ns	65 ns	65 ns
Maximum seat height	4.2 mm	4.7 mm	1.1 mm	1.1 mm
Maximum supply voltage (Vsup)	6 V	5.5 V	5.5 V	5.5 V
Minimum supply voltage (Vsup)	2 V	4.5 V	4.5 V	4.5 V
Nominal supply voltage (Vsup)	5 V	5 V	5 V	5 V
surface mount	NO	NO	YES	YES
technology	CMOS	CMOS	CMOS	CMOS
Temperature level	AUTOMOTIVE	AUTOMOTIVE	AUTOMOTIVE	AUTOMOTIVE
Terminal form	THROUGH-HOLE	THROUGH-HOLE	GULL WING	GULL WING
Terminal pitch	2.54 mm	2.54 mm	0.65 mm	0.65 mm
Terminal location	DUAL	DUAL	DUAL	DUAL
Trigger type	POSITIVE EDGE	POSITIVE EDGE	POSITIVE EDGE	POSITIVE EDGE
width	7.62 mm	7.62 mm	4.4 mm	4.4 mm
minfmax	13 MHz	13 MHz	13 MHz	13 MHz
Is it Rohs certified?	conform to	conform to	conform to	-
Maker	NXP	NXP	NXP	-
package instruction	DIP, DIP16,.3	DIP, DIP16,.3	-	TSSOP,
JESD-609 code	e4	e4	e4	-
Load capacitance (CL)	50 pF	50 pF	50 pF	-
Peak Reflow Temperature (Celsius)	260	260	240	-
Certification status	Not Qualified	Not Qualified	Not Qualified	-
Terminal surface	NICKEL PALLADIUM GOLD	NICKEL PALLADIUM GOLD	NICKEL PALLADIUM GOLD	-
Maximum time at peak reflow temperature	30	30	30	-
Base Number Matches	1	1	1	-

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