INTEGRATED CIRCUITS
74LVT534
3.3 V Octal D-type flip-flop; inverting
(3-State)
Product data
Supersedes data of 1998 Feb 19
2004 Aug 25
Philips
Semiconductors
Philips Semiconductors
Product data
3.3 V Octal D-type flip-flop, inverting (3-State)
74LVT534
FEATURES
•
3-State outputs for bus interfacing
•
Common output enable
•
TTL input and output switching levels
•
Input and output interface capability to systems at 5 V supply
•
Bus-hold data inputs eliminate the need for external pull-up
•
Live insertion/extraction permitted
•
No bus current loading when output is tied to 5 V bus
•
Power-up 3-State
•
Power-up reset
•
Latch-up protection exceeds 500mA per JEDEC Std 17
•
ESD protection exceeds 2000 V per MIL STD 883 Method 3015
and 200 V per Machine Model
resistors to hold unused inputs
DESCRIPTION
The LVT534 is a high-performance BiCMOS product designed for
V
CC
operation at 3.3 V.
This device is an 8-bit, edge triggered register coupled to eight
3-State output buffers. The two sections of the device are controlled
independently by the clock (CP) and Output Enable (OE) control
gates. The state of each D input (one set-up time before the
LOW-to-HIGH clock transition) is transferred to the corresponding
flip-flop’s Q output.
The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors. The
active-LOW Output Enable (OE) controls all eight 3-State buffers
independent of the clock operation.
When OE is LOW, the stored data appears at the outputs. When OE
is HIGH, the outputs are in the high-impedance “off” state, which
means they will neither drive nor load the bus.
QUICK REFERENCE DATA
SYMBOL
t
PLH
t
PHL
C
IN
C
OUT
I
CCZ
PARAMETER
Propagation delay
CP to Qn
Input capacitance
Output capacitance
Total supply current
CONDITIONS
T
amb
= 25
°C;
GND = 0 V
C
L
= 50 pF;
V
CC
= 3.3 V
V
I
= 0 V or 3.0 V
Outputs disabled;
V
I/O
= 0 V or 3.0 V
Outputs disabled;
V
CC
= 3.6 V
TYPICAL
3.0
3.5
4
7
0.13
UNIT
ns
pF
pF
mA
ORDERING INFORMATION
PACKAGES
20-Pin Plastic SOL
20-Pin Plastic SSOP Type II
20-Pin Plastic TSSOP Type I
TEMPERATURE RANGE
–40
°C
to +85
°C
–40
°C
to +85
°C
–40
°C
to +85
°C
TYPE NUMBER
74LVT534D
74LVT534DB
74LVT534PW
DWG NUMBER
SOT163-1
SOT339-1
SOT360-1
PIN CONFIGURATION
PIN DESCRIPTION
PIN NUMBER
SYMBOL
OE
D0 to D7
Q0 to Q7
CP
GND
V
CC
FUNCTION
Output enable input (active-LOW)
Data inputs
Inverting 3-State outputs
Clock pulse input (active rising
edge)
Ground (0 V)
Positive supply voltage
1
3, 4, 7, 8,
13, 14, 17, 18
2, 5, 6, 9,
12, 15, 16, 19
11
10
20
OE
Q0
1
2
20 V
CC
19 Q7
18 D7
17 D6
16 Q6
15 Q5
14 D5
13 D4
12 Q4
11 CP
D0 3
D1 4
Q1
Q2
5
6
D2 7
D3 8
Q3
9
GND 10
SA00161
2004 Aug 25
2
Philips Semiconductors
Product data
3.3 V Octal D-type flip-flop, inverting (3-State)
74LVT534
LOGIC SYMBOL
LOGIC SYMBOL (IEEE/IEC)
1
11
C1
EN
3
4
7
8
13
14
17
18
3
D0
11
CP
D1
D2
D3
D4
D5
D6
D7
4
7
1
OE
Q0 Q1 Q2 Q3
Q4 Q5 Q6 Q7
8
13
14
2
5
6
9
12
15
16
19
17
1D
2
5
6
9
12
15
16
19
SA00162
18
SA00163
FUNCTION TABLE
INPUTS
OE
L
L
L
H
H
CP
↑
↑
↑
↑
↑
Dn
l
h
X
X
Dn
INTERNAL
REGISTER
L
H
NC
NC
Dn
OUTPUTS
Q0 to Q7
H
L
NC
Z
Z
OPERATING
MODE
Latch and read
register
Hold
Disable
outputs
H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH
clock transition
L = LOW voltage level
l = LOW voltage level one set-up time prior to the LOW-to-HIGH
clock transition
NC= No change
X = Don’t care
Z = high-impedance “off” state
↑
= LOW-to-HIGH clock transition
↑
= not a LOW-to-HIGH clock transition
LOGIC DIAGRAM
D0
2
D1
3
D2
4
D3
5
D4
6
D5
7
D6
8
D7
9
D
D
D
D
D
D
D
D
CP Q
CP Q
CP Q
CP Q
CP Q
CP Q
CP Q
CP Q
11
CP
1
OE
19
Q0
18
Q1
17
Q2
16
Q3
15
Q4
14
Q5
13
Q6
12
Q7
SV00168
2004 Aug 25
3
Philips Semiconductors
Product data
3.3 V Octal D-type flip-flop, inverting (3-State)
74LVT534
ABSOLUTE MAXIMUM RATINGS
1, 2
SYMBOL
V
CC
I
IK
V
I
I
OK
V
OUT
I
O
OUT
T
stg
PARAMETER
DC supply voltage
DC input diode current
DC input voltage
3
DC output diode current
DC output voltage
3
DC output current
Storage temperature range
V
O
< 0 V
Output in Off or HIGH state
Output in LOW state
Output in HIGH state
V
I
< 0 V
CONDITIONS
RATING
–0.5 to +4.6
–50
–0.5 to +7.0
–50
–0.5 to +7.0
128
–64
–65 to +150
mA
°C
UNIT
V
mA
V
mA
V
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150
°C.
3. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
V
CC
V
I
V
IH
V
IL
I
OH
I
O
OL
∆t/∆v
T
amb
DC supply voltage
Input voltage
HIGH-level input voltage
Input voltage
HIGH-level output current
LOW-level output current
LOW-level output current; current duty cycle
≤
50 %, f
≥
1 kHz
Input transition rise or fall rate; outputs enabled
Operating free-air temperature range
PARAMETER
MIN
2.7
0
2.0
–
–
–
–
–
–40
MAX
3.6
5.5
–
0.8
–32
32
64
10
+85
mA
ns/V
°C
UNIT
V
V
V
V
mA
2004 Aug 25
4
Philips Semiconductors
Product data
3.3 V Octal D-type flip-flop, inverting (3-State)
74LVT534
DC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
T
amb
= –40° C to +85
°C
MIN
V
IK
V
OH
Input clamp voltage
V
CC
= 2.7 V; I
IK
= –18 mA
V
CC
= 2.7 V to 3.6 V; I
OH
= –100
µA
HIGH-level output voltage
V
CC
= 2.7 V; I
OH
= –8 mA
V
CC
= 3.0 V; I
OH
= –32 mA
V
CC
= 2.7 V; I
OL
= 100
µA
V
CC
= 2.7 V; I
OL
= 24 mA
V
OL
LOW-level output voltage
V
CC
= 3.0 V; I
OL
= 16 mA
V
CC
= 3.0 V; I
OL
= 32 mA
V
CC
= 3.0 V; I
OL
= 64 mA
V
RST
Power-up output low voltage
5
V
CC
= 3.6 V; I
O
= 1 mA; V
I
= GND or V
CC
V
CC
= 0 V or 3.6 V; V
I
= 5.5 V
I
I
Input leakage current
V
CC
= 3.6 V; V
I
= V
CC
or GND
V
CC
= 3.6 V; V
I
= V
CC
V
CC
= 3.6 V; V
I
= 0 V
I
OFF
I
HOLD
Output off current
Bus Hold current A inputs
7
V
CC
= 0 V; V
I
or V
O
= 0 V to 4.5 V
V
CC
= 3 V; V
I
= 0.8 V
V
CC
= 3 V; V
I
= 2.0 V
V
CC
= 0 V to 3.6 V; V
CC
= 3.6 V
I
EX
I
PU/PD
I
OZH
I
OZL
I
CCH
I
CCL
I
CCZ
∆I
CC
Additional supply current per
input pin
2
Quiescent supply current
3
Current into an output in the
HIGH state when V
O
> V
CC
Power-up/down 3-State
output current
3
3-State output HIGH current
3-State output LOW current
V
O
= 5.5 V; V
CC
= 3.0 V
V
CC
≤
1.2 V; V
O
= 0.5 V to V
CC
; V
I
= GND or V
CC
;
OE/OE = Don’t care
V
CC
= 3.6 V; V
O
= 3 V; V
I
= V
IL
or V
IH
V
CC
= 3.6 V; V
O
= 0.5 V; V
I
= V
IL
or V
IH
V
CC
= 3.6 V; Outputs HIGH; V
I
= GND or V
CC
;
I
O
= 0 mA
V
CC
= 3.6 V; Outputs LOW, V
I
= GND or V
CC
;
I
O
= 0 mA
V
CC
= 3.6 V; Outputs Disabled; V
I
= GND or V
CC
;
I
O
= 0 mA
6
V
CC
= 3 V to 3.6 V; One input at V
CC
– 0.6 V;
Other inputs at V
CC
or GND
Control pins
Data pins
4
–
V
CC
– 0.2
2.4
2.0
–
–
–
–
–
–
–
–
–
–
–
75
–75
±
500
–
–
–
–
–
–
–
–
TYP
1
–0.9
V
CC
– 0.1
2.5
2.2
0.1
0.3
0.25
0.3
0.4
0.13
1
±
0.1
0.1
–1
1
150
–150
–
60
1
1
1
0.13
3
0.13
0.1
MAX
–1.2
–
–
–
0.2
0.5
0.4
0.5
0.55
0.55
10
±
1
1
–5
±
100
–
–
–
125
±
100
5
–5
0.19
12
0.19
0.2
V
V
V
V
V
V
V
V
V
V
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
mA
mA
mA
mA
UNIT
NOTES:
1. All typical values are at V
CC
= 3.3 V and T
amb
= 25
°C.
2. This is the increase in supply current for each input at the specified voltage level other than V
CC
or GND.
3. This parameter is valid for any V
CC
between 0 V and 1.2 V with a transition time of up to 10 msec. From V
CC
= 1.2 V to V
CC
= 3.3 V
±
0.3 V
a transition time of 100
µsec
is permitted. This parameter is valid for T
amb
= 25
°C
only.
4. Unused pins at V
CC
or GND.
5. For valid test results, data must not be loaded into the flip-flops (or latches) after applying power.
6. I
CCZ
is measured with outputs pulled to V
CC
or down to GND.
7. This is the bus hold overdrive current required to force the input to the opposite logic state.
2004 Aug 25
5
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