INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
•
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT251
8-input multiplexer; 3-state
Product specification
File under Integrated Circuits, IC06
December 1990
Philips Semiconductors
Product specification
8-input multiplexer; 3-state
FEATURES
•
True and complement outputs
•
Both outputs are 3-state for further multiplexer
expansion
•
Multifunction capability
•
Permits multiplexing from n-lines to one line
•
Output capability: standard
•
I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT251 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
= 6 ns
74HC/HCT251
The 74HC/HCT251 are the logic implementations of
single-pole 8-position switches with the state of three
select inputs (S
0
, S
1
, S
2
) controlling the switch positions.
Assertion (Y) and negation (Y) outputs are both provided.
The output enable input (OE) is active LOW. The logic
function provided at the output, when activated, is:
Y = OE.(I
0
.S
0
.S
1
.S
2
+
I
1
.S
0
.S
1
.S
2
+
+
I
2
.S
0
.S
1
.S
2
+
I
3
.S
0
.S
1
.S
2
+
+
I
4
.S
0
.S
1
.S
2
+
I
5
.S
0
.S
1
.S
2
+
+
I
6
.S
0
.S
1
.S
2
+
I
7
.S
0
.S
1
.S
2
)
Both outputs are in the high impedance OFF-state (Z)
when the output enable input is HIGH, allowing multiplexer
expansion by tying the outputs.
TYPICAL
SYMBOL
t
PHL
/ t
PLH
PARAMETER
propagation delay
I
n
to Y
I
n
to Y
S
n
to Y
S
n
to Y
C
I
C
PD
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW):
P
D
= C
PD
×
V
CC2
×
f
i
+ ∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
2. For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
−
1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”.
input capacitance
power dissipation capacitance per package
notes 1 and 2
CONDITIONS
HC
C
L
= 15 pF; V
CC
= 5 V
15
17
20
21
3.5
44
19
19
20
21
3.5
46
ns
ns
ns
ns
pF
pF
HCT
UNIT
December 1990
2
Philips Semiconductors
Product specification
8-input multiplexer; 3-state
PIN DESCRIPTION
PIN NO.
4, 3, 2, 1, 15, 14, 13, 12
5
6
7
8
11, 10, 9
16
SYMBOL
I
0
to I
7
Y
Y
OE
GND
S
0
, S
1
, S
2
V
CC
NAME AND FUNCTION
multiplexer inputs
multiplexer output
74HC/HCT251
complementary multiplexer output
3-state output enable input (active LOW)
ground (0 V)
select inputs
positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
3
Philips Semiconductors
Product specification
8-input multiplexer; 3-state
FUNCTION TABLE
INPUTS
OE
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
Note
1. H = HIGH voltage level
L = LOW voltage level
X = don’t care
Z = high impedance OFF-state
S
2
X
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
S
1
X
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
S
0
X
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
I
0
X
L
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
I
1
X
X
X
L
H
X
X
X
X
X
X
X
X
X
X
X
X
I
2
X
X
X
X
X
L
H
X
X
X
X
X
X
X
X
X
X
I
3
X
X
X
X
X
X
X
L
H
X
X
X
X
X
X
X
X
I
4
X
X
X
X
X
X
X
X
X
L
H
X
X
X
X
X
X
I
5
X
X
X
X
X
X
X
X
X
X
X
L
H
X
X
X
X
I
6
X
X
X
X
X
X
X
X
X
X
X
X
X
L
H
X
X
74HC/HCT251
OUTPUTS
I
7
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
H
Y
Z
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
Y
Z
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
Fig.4 Functional diagram.
Fig.5 Logic diagram.
December 1990
4
Philips Semiconductors
Product specification
8-input multiplexer; 3-state
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
I
CC
category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
r
= t
f
= 6 ns; C
L
= 50 pF
T
amb
(°C)
74HC
SYMBOL PARAMETER
+25
−40
to
+85
max.
215
43
37
220
44
37
255
51
43
255
51
43
175
35
30
170
35
30
95
19
16
−40
to
+125
min. max.
255
51
43
265
53
45
310
62
53
310
62
53
210
42
36
210
42
36
110
22
19
ns
74HC/HCT251
TEST CONDITIONS
UNIT V
WAVEFORMS
CC
(V)
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
Fig.6
min. typ. max. min.
t
PHL
/ t
PLH
propagation delay
I
n
to Y
propagation delay
I
n
to Y
propagation delay
S
n
to Y
propagation delay
S
n
to Y
3-state output enable time
OE to Y, Y
3-state output disable time
OE to Y, Y
output transition time
50
18
14
55
20
16
66
24
19
69
25
20
36
13
10
39
14
11
19
7
6
170
34
29
175
35
30
205
41
35
205
41
35
140
28
24
140
28
24
75
15
13
t
PHL
/ t
PLH
ns
Fig.7
t
PHL
/ t
PLH
ns
Fig.6
t
PHL
/ t
PLH
ns
Fig.7
t
PZH
/ t
PZL
ns
Fig.7
t
PHZ
/ t
PLZ
ns
Fig.7
t
THL
/ t
TLH
ns
Figs 6 and 7
December 1990
5
Embedded System
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