SC28L201
3.3 V, 5 V UART, 3.125 Mbit/s, with 256-byte FIFO
Rev. 01 — 31 October 2005
Product data sheet
1. General description
The SC28L201 is a high performance UART. Its functional and programming features
closely match but greatly extend those of previous Philips UARTs. Its configuration on
power-up is similar that of the SC26C92. Its differences from the previous Philips UARTs
are: 256-character receiver, 256-character transmit FIFOs, 3.3 V and 5 V compatibility,
8 I/O ports for arbitrating interrupt system and overall faster bus and data speeds and is
fabricated in an advanced 0.5 micron CMOS process.
It is a member of the IMPACT line of data communications parts.
Pin programming will allow the device to operate with either the Motorola or Intel bus
interface by changing the function of some pins (reset is inverted, DACKN, and IACKN
enabled, for example).
The Philips Semiconductors SC28L201 Universal Asynchronous Receiver/Transmitter
(UART) is a single-chip CMOS-LSI communications device that provides a full-duplex
asynchronous receiver/transmitter channel in a single package. It interfaces directly with
microprocessors and may be used in a polled or interrupt driven system. The use of the
Interrupt system provides intelligent interrupt vectors.
The operating mode and data format of the channel may be programmed independently.
Additionally, the receiver and transmitter can select its operating speed as one of
twenty-seven fixed baud rates; a 16× clock derived from one of two programmable
counter/timers, or an external 1× or 16× clock. The baud rate generator and counter/timer
can operate directly from a crystal or from external clock inputs. The ability to
independently program the operating speed of the receiver and transmitter make the
UART particularly attractive for dual-speed channel applications such as clustered
terminal systems and bridges.
Each receiver and transmitter is buffered by 256-character FIFOs to nearly eliminate the
potential of receiver overrun, transmitter underrun and to reduce interrupt overhead in
interrupt driven systems. In addition, a flow control capability (Xon/Xoff and RTS/CTS) is
provided to disable a remote transmitter when the receiver buffer is full.
Also provided on the SC28L201 is a multipurpose 8-bit I/O for the channel. These can be
used as general-purpose I/O ports or can be assigned specific functions (such as clock
inputs or status and interrupt outputs) under program control. Normally they will be used
for modem control and DMA interface. All ports have change of state detectors and input
sections are always active making output signals available to the internal circuits and the
control processor.
The SC28L201 is available in a TSSOP48 package. For other package options, contact
Philips.
Philips Semiconductors
SC28L201
3.3 V, 5 V UART, 3.125 Mbit/s, with 256-byte FIFO
2. Features
s
Member of IMPACT family: 3.3 V or 5.0 V,
−40 °C
to +85
°C
and 80xxx or 68000 bus
interface (I/M modes)
s
Bit-by-bit real time transmission error check for high data integrity systems
s
Full-duplex independent asynchronous receiver/transmitter
s
256 character FIFOs for receiver and transmitter
s
Powers up to 9600 baud, 8 bits, no parity, 1 stop bit, interrupt disabled, all I/O set to
input
s
Pin programming to 68000 or 80xxx bus interface
s
Three character recognition system, used as:
x
General purpose character recognition
x
Xon/Xoff character recognition
x
Address recognition Wake-up (multi-drop or 9-bit) mode
x
System provides 4 levels of automation on a recognition event
s
Programmable data format
x
5 to 8 data bits plus parity and 9-bit mode
x
Odd, even, no parity, or force parity
x
9
⁄
16
, 1, 1.5 or 2 stop bits
s
16-bit programmable Counter/Timer
s
Programmable baud rate for receiver and transmitter selectable from:
x
27 fixed rates: 50 Bd to 2.0 MBd (includes MIDI rate)
x
Other baud rates via external clocks and C/T
x
Programmable user-defined rates derived from a programmable Counter/Timer
x
External 1× or 16× clock
s
Parity, framing, and overrun error detection
s
Line break detection and generation; false start bit detection
s
Programmable channel mode
x
Normal (full-duplex)
x
Automatic echo
x
Local loopback
x
Remote loopback
x
Multi-drop mode (also called ‘Wake-up’ or ‘9-bit’)
s
Multifunction 13-bit I/O input port
x
Can serve as clock or control inputs
x
Change-of-state detection on eight inputs
x
Inputs have typically > 100 MΩ pull-up resistors
x
Modem and DMA interface
s
Versatile arbitrating interrupt system
x
Interrupt system totally supports single query polling
x
Output port can be configured to provide a total of up to six separate interrupt type
outputs that may be wire-ORed (switched to open-drain)
x
Each FIFO can be independently programmed for any of 256 interrupt levels
x
Watchdog timer for receiver
s
Maximum data transfer rates: 1× clock = 3 Mbit/s; 16× clock = 3.125 Mbit/s
9397 750 13138
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 31 October 2005
2 of 110
Philips Semiconductors
SC28L201
3.3 V, 5 V UART, 3.125 Mbit/s, with 256-byte FIFO
s
s
s
s
s
s
s
Automatic Wake-up mode for multi-drop applications
Start-end break interrupt/status
Detects break which originates in the middle of a character
On-chip crystal oscillator
Power-down mode at less than 10
µA
Receiver Time-out mode
Single +3.3 V
±
10 % or +5 V
±
10 % power supply
3. Ordering information
Table 1:
Ordering information
V
DD
= +3.3 V
±
10 % or V
DD
= +5.0 V
±
10 %; T
amb
=
−
40
°
C to +85
°
C
Type number
SC28L201A1DGG
Package
Name
TSSOP48
Description
plastic thin shrink small outline package; 48 leads; body width 6.1 mm
Version
SOT362-1
9397 750 13138
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 31 October 2005
3 of 110
Philips Semiconductors
SC28L201
3.3 V, 5 V UART, 3.125 Mbit/s, with 256-byte FIFO
4. Block diagram
SC28L201 (80xxx mode)
8
D0 to D7
BUS BUFFER
DATA CHANNEL
256-BYTE
TRANSMIT FIFO
TXD
RDN
WRN
CEN
A0 to A6
RESET
7
OPERATION
CONTROL
ADDRESS
DECODE
R/W CONTROL
TRANSMIT
SHIFT REGISTER
256-BYTE
RECEIVE FIFO
WATCHDOG
TIMER
RECEIVE
SHIFT REGISTER
RXD
INTERRUPT
ARBITRATION
IRQN
IMR
INTERNAL DATA BUS
ISR
GP
control
timing
MR0, 1, 2, 3
CR
SR
SOFTWARE
FLOW CONTROL
I/O PORT A
CHANGE-OF-
STATE
DETECTORS (4)
TIMING
BAUD RATE
GENERATOR
CLOCK
SELECTORS
COUNTER/
TIMER
XTAL
OSCILLATOR
CSR
ACR
CTL
CTU
8
I/O7A to I/O0A
IOPCR
ACR
X1/SCLK
X2
I/O PORT B
FUNCTION
SELECT LOGIC
IOPCR
OPR
5
I/O0B
I/O4B to I/O2B
I/O6B
002aab569
Fig 1. Block diagram of SC28L201 (80xxx mode)
9397 750 13138
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 31 October 2005
4 of 110
Philips Semiconductors
SC28L201
3.3 V, 5 V UART, 3.125 Mbit/s, with 256-byte FIFO
SC28L201 (68000 mode)
8
D0 to D7
BUS BUFFER
DATA CHANNEL
256-BYTE
TRANSMIT FIFO
TXD
R/WN
IACKN
CEN
A0 to A6
RESETN
7
OPERATION
CONTROL
ADDRESS
DECODE
R/W CONTROL
TRANSMIT
SHIFT REGISTER
256-BYTE
RECEIVE FIFO
WATCHDOG
TIMER
RECEIVE
SHIFT REGISTER
RXD
INTERRUPT
ARBITRATION
IRQN
DACKN
IMR
INTERNAL DATA BUS
ISR
GP
control
timing
MR0, 1, 2, 3
CR
SR
SOFTWARE
FLOW CONTROL
I/O PORT A
CHANGE-OF-
STATE
DETECTORS (4)
TIMING
BAUD RATE
GENERATOR
CLOCK
SELECTORS
COUNTER/
TIMER
XTAL
OSCILLATOR
CSR
ACR
CTL
CTU
8
I/O7A to I/O0A
IOPCR
ACR
X1/SCLK
X2
I/O PORT B
FUNCTION
SELECT LOGIC
IOPCR
5
I/O0B
I/O4B to I/O2B
I/O6B
002aab570
Fig 2. Block diagram of SC28L201 (68000 mode)
9397 750 13138
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 31 October 2005
5 of 110