74FST3253
Dual 4:1 Multiplexer/
Demultiplexer Bus Switch
The ON Semiconductor 74FST3253 is a dual 4:1, high performance
multiplexer/demultiplexer bus switch. The device is CMOS TTL
compatible when operating between 4 and 5.5 Volts. The device
exhibits extremely low R
ON
and adds nearly zero propagation delay.
The device adds no noise or ground bounce to the system.
Features
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MARKING
DIAGRAMS
16
1
SOIC−16
D SUFFIX
CASE 751B
16
FST3253
AWLYWW
1
16
16
1
TSSOP−16
DT SUFFIX
CASE 948F
A
L, WL
Y
W, WW
=
=
=
=
FST
3253
ALYW
1
Assembly Location
Wafer Lot
Year
Work Week
•
•
•
•
•
•
•
•
R
ON
t
4
W
Typical
Less Than 0.25 ns−Max Delay Through Switch
Nearly Zero Standby Current
No Circuit Bounce
Control Inputs are TTL/CMOS Compatible
Pin−For−Pin Compatible With QS3253, FST3253, CBT3253
Popular Packages: TSSOP−16, SOIC−16
All Devices in Package TSSOP are Inherently Pb−Free*
OE
1
S1
1B
4
1B
3
1B
2
1B
1
1A
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC
OE
2
S
0
2B
4
2B
3
2B
2
2B
1
2A
PIN NAMES
Pin
OE
1
, OE
2
S
0
, S
1
A
B
1
, B
2
, B
3
, B
4
Description
Bus Switch Enables
Select Inputs
Bus A
Bus B
Figure 1. 16−Lead
Pinout
S
1
X
X
L
L
H
H
S
0
OE
1
OE
2
X
X
L
H
L
H
H
X
L
L
L
L
X
H
L
L
L
L
Function
Disconnect 1A
Disconnect 2A
A = B
1
A = B
2
A = B
3
A = B
4
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
Figure 2. Truth Table
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
©
Semiconductor Components Industries, LLC, 2006
June, 2006
−
Rev. 4
1
Publication Order Number:
74FST3253/D
74FST3253
1A
1B
1
1B
2
1B
3
1B
4
2A
2B
1
2B
2
2B
3
2B
4
FLOW CONTROL
OE
1
OE
2
S
0
S
1
Figure 3. Logic Diagram
ORDERING INFORMATION
Device Order Number
74FST3253D
74FST3253DR2
74FST3253DT
74FST3253DTR2
Package
SOIC−16
SOIC−16
TSSOP−16*
(Pb−Free)
TSSOP−16*
(Pb−Free)
Shipping
†
48 Units / Rail
2500 Units / Tape & Reel
96 Units / Rail
2500 Units / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
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2
74FST3253
MAXIMUM RATINGS
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
I
CC
I
GND
T
STG
T
L
T
J
q
JA
MSL
F
R
V
ESD
DC Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Diode Current
DC Output Diode Current
DC Output Sink Current
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature Range
Lead Temperature, 1 mm from Case for 10 Seconds
Junction Temperature Under Bias
Thermal Resistance
Moisture Sensitivity
Flammability Rating
ESD Withstand Voltage
Oxygen Index: 28 to 34
Human Body Model (Note 1)
Machine Model (Note 2)
Charged Device Model (Note 3)
Above V
CC
and Below GND at 85_C (Note 4)
SOIC
TSSOP
V
I
t
GND
V
O
t
GND
Parameter
Value
*0.5
to
)7.0
*0.5
to
)7.0
*0.5
to
)7.0
*50
*50
128
$100
$100
*65
to
)150
260
)150
125
170
Level 1
UL 94 V−0 @ 0.125 in
u2000
u200
N/A
$500
V
Unit
V
V
V
mA
mA
mA
mA
mA
_C
_C
_C
_C/W
I
Latchup
Latchup Performance
mA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Tested to EIA/JESD22−A114−A.
2. Tested to EIA/JESD22−A115−A.
3. Tested to JESD22−C101−A.
4. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
I
V
O
T
A
Dt/DV
Supply Voltage
Input Voltage
Output Voltage
Operating Free−Air Temperature
Input Transition Rise or Fall Rate
Switch I/O
Switch Control Input
V
CC
= 5.0 V
$
0.5 V
Parameter
Operating, Data Retention Only
(Note )
(HIGH or LOW State)
Min
4.0
0
0
*40
0
Max
5.5
5.5
5.5
)85
DC
5
Unit
V
V
V
_C
ns/V
5. Unused control inputs may not be left open. All control inputs must be tied to a high or low logic input voltage level.
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3
74FST3253
DC ELECTRICAL CHARACTERISTICS
V
CC
Symbol
V
IK
V
IH
V
IL
I
I
I
OZ
R
ON
Parameter
Clamp Diode Resistance
High−Level Input Voltage
Low−Level Input Voltage
Input Leakage Current
OFF−STATE Leakage Current
Switch On Resistance (Note 6)
0
v
V
IN
v
5.5 V
0
v
A, B
v
V
CC
V
IN
= 0 V, I
IN
= 64 mA
V
IN
= 0 V, I
IN
= 30 mA
V
IN
= 2.4 V, I
IN
= 15 mA
V
IN
= 2.4 V, I
IN
= 15 mA
I
CC
DI
CC
Quiescent Supply Current
Increase In I
CC
per Input
V
IN
= V
CC
or GND, I
OUT
= 0
One input at 3.4 V, Other inputs at V
CC
or GND
I
IN
=
*18mA
Conditions
(V)
4.5
4.0 to 5.5
4.0 to 5.5
5.5
5.5
4.5
4.5
4.5
4.0
5.5
5.5
4
4
8
11
2.0
0.8
$1.0
$1.0
7
7
15
20
3
2.5
mA
mA
T
A
=
*40_C
to
)85_C
Min
Typ*
Max
*1.2
Unit
V
V
V
mA
mA
W
*Typical values are at V
CC
= 5.0 V and T
A
= 25_C.
6. Measured by the voltage drop between A and B pins at the indicated current through the switch. On resistance is determined by the lower
of the voltages on the two (A or B) pins.
AC ELECTRICAL CHARACTERISTICS
T
A
=
*40_C
to
)85_C
C
L
= 50 pF, RU = RD = 500
W
V
CC
= 4.5−5.5 V
Symbol
t
PHL
, t
PLH
t
PZH
, t
PZL
t
PHZ
, t
PLZ
Parameter
Prop Delay Bus to Bus (Note 7)
Prop Delay, Select to Bus A
Output Enable Time, Select to Bus B
Output Enable Time, I
OE
to Bus A, B
Output Disable Time, Select to Bus B
Output Disable Time, I
OE
to Bus A, B
V
I
= 7 V for t
PZL
V
I
= OPEN for t
PZH
V
I
= 7 V for t
PLZ
V
I
= OPEN for t
PHZ
Conditions
V
I
= OPEN
1.0
1.0
1.0
1.0
1.0
Min
Max
0.25
5.3
5.3
5.3
5.8
5.5
V
CC
= 4.0 V
Min
Max
0.25
6.3
6.0
6.2
6.2
6.2
ns
ns
Unit
ns
7. This parameter is guaranteed by design but is not tested. The bus switch contributes no propagation delay other than the RC delay of the
typical On resistance of the switch and the 50 pF load capacitance, when driven by an ideal voltage source (zero output impedance).
CAPACITANCE
(Note 8)
Symbol
C
IN
C
I/O
C
I/O
Parameter
Control Pin Input Capacitance
A Port Input/Output Capacitance
B Port Input/Output Capacitance
V
CC
= 5.0 V
V
CC
, OE = 5.0 V
V
CC
, OE = 5.0 V
Conditions
Typ
3
13
5
Max
Unit
pF
pF
pF
8. T
A
=
)25_C,
f = 1 MHz, Capacitance is characterized but not tested.
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4
74FST3253
AC Loading and Waveforms
V
I
FROM
OUTPUT
UNDER
TEST
500
W
C
L
*
500
W
NOTES:
1. Input driven by 50
W
source terminated in 50
W.
2. CL includes load and stray capacitance.
*C
L
= 50 pF
Figure 4. AC Test Circuit
t
f
= 2.5 nS
90 %
SWITCH
INPUT
1.5 V
10 %
t
PLH
1.5 V
90 %
1.5 V
t
f
= 2.5 nS
3.0 V
10 %
t
PLH
GND
V
OH
OUTPUT
1.5 V
V
OL
Figure 5. Propagation Delays
t
f
= 2.5 nS
t
f
= 2.5 nS
ENABLE
INPUT
90 %
1.5 V
10 %
t
PZL
OUTPUT
1.5 V
t
PZH
10 %
90 %
1.5 V
GND
t
PZL
3.0 V
V
OL
+ 0.3 V
V
OL
t
PHZL
V
OH
1.5 V
OUTPUT
V
OH
−
0.3 V
Figure 6. Enable/Disable Delays
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