Maximum PIOA or PIOB Pin Current...................................20mA
Maximum Current Through GND Pin ..................................40mA
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-55°C to +125°C
Soldering Temperature...........................Refer to the IPC/JEDEC
J-STD-020 Specification.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(T
A
= -40°C to +85°C.) (Note 1)
PARAMETER
POWER SUPPLY
Supply Voltage
Supply Current (Note 3)
Standby Current
IO PIN: GENERAL DATA
1-Wire Pullup Voltage (Note 2)
1-Wire Pullup Resistance
Input Capacitance
Input Load Current
High-to-Low Switching Threshold
Input Low Voltage (Notes 2, 8)
Low-to-High Switching Threshold
(Notes 3, 6, 9)
Switching Hysteresis
(Notes 3, 6, 10)
Output Low Voltage (Note 11)
Recovery Time
(Notes 2, 12)
V
PUP
R
PUP
C
IO
I
L
V
TL
V
IL
V
TH
V
HY
V
OL
Local power
Parasite power
(Notes 2, 4)
(Notes 3, 5)
IO pin at V
PUP
(Notes 3, 6, 7)
Parasite powered
V
DD
powered (Note 3)
Parasite power
Parasite power
At 4mA
Standard speed, R
PUP
= 2.2k
t
REC
Overdrive speed, R
PUP
= 2.2k
Overdrive speed, directly prior to reset
pulse; R
PUP
= 2.2k
Standard speed
Overdrive speed
Standard speed
Overdrive speed
Standard speed
Overdrive speed
5
2
5
0.5
65
8
480
48
640
80
5.0
μs
μs
μs
1.0
0.21
0.1
0.46
3.0
3.0
0.3
V
DD
5.5
2.2
1000
1.5
V
PUP
-
1.9V
0.5
0.7
V
PUP
-
1.1V
1.7
0.4
V
k
pF
μA
V
V
V
V
V
V
DD
I
DD
I
DDS
(Note 2)
V
DD
= +5.5V
V
DD
= +5.5V
3.0
5.5
1.5
1.5
V
mA
μA
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Rising-Edge Hold-Off Time
(Notes 3, 13)
Time-Slot Duration
(Notes 2, 14)
t
REH
t
SLOT
Not applicable (0)
IO PIN: 1-Wire RESET, PRESENCE-DETECT CYCLE
Reset Low Time (Note 2)
t
RSTL
μs
2
Maxim Integrated
DS28EA00
1-Wire Digital Thermometer with
Sequence Detect and PIO
ELECTRICAL CHARACTERISTICS (continued)
(T
A
= -40°C to +85°C.) (Note 1)
PARAMETER
Presence-Detect High Time
Presence-Detect Fall Time
(Notes 3, 15)
Presence-Detect Low Time
Presence-Detect Sample Time
(Notes 2, 16)
IO PIN: 1-Wire WRITE
Write-Zero Low Time
(Notes 2, 17)
Write-One Low Time
(Notes 2, 17)
IO PIN: 1-Wire READ
Read Low Time (Notes 2, 18)
Read Sample Time (Notes 2, 18)
PIO PINS
Input Low Voltage
Input High Voltage (Note 2)
Input Load Current (Note 19)
Output Low Voltage (Note 11)
Chain-On Pullup Impedance
EEPROM
Programming Current
Programming Time
Write/Erase Cycles (Endurance)
(Notes 22, 23)
Data Retention (Notes 24, 25)
TEMPERATURE CONVERTER
Conversion Current
I
CONV
(Notes 3, 20)
12-bit resolution (1/16°C)
Conversion Time (Note 26)
t
CONV
11-bit resolution (1/8°C)
10-bit resolution (1/4°C)
9-bit resolution (1/2°C)
Conversion Error
Converter Drift
D
SYMBOL
t
PDH
t
FPD
t
PDL
t
MSP
CONDITIONS
Standard speed
Overdrive speed
Standard speed
Overdrive speed
Standard speed
Overdrive speed
Standard speed
Overdrive speed
Standard speed
Overdrive speed
Standard speed
Overdrive speed
Standard speed
Overdrive speed
Standard speed
Overdrive speed
(Note 2)
V
X
= Max(V
PUP
, V
DD
)
Pin at GND
At 4mA
(Note 3)
(Notes 3, 20)
(Note 21)
At +25°C
-40°C to +85°C
At +85°C (worst case)
MIN
15
2
1.125
0
60
8
68.1
7.3
60
6
5
1
5
1
t
RL
+
t
RL
+
TYP
MAX
60
6
8.1
1.3
240
24
75
10
120
16
15
2
15 -
2-
15
2
0.3
UNITS
μs
μs
μs
μs
t
W0L
t
W1L
μs
μs
t
RL
t
MSR
μs
μs
V
ILP
V
IHP
I
LP
V
OLP
R
CO
I
PROG
t
PROG
N
CY
t
DR
V
V
μA
V
X
- 1.6
-1.1
0.4
20
40
60
1.5
10
200,000
50,000
10
1.5
750
375
187.5
93.75
-0.5
-0.5
-0.2
+0.5
+2.0
+0.2
V
k
mA
ms
—
Years
mA
ms
-10°C to +85°C
Below -10°C (Note 3)
(Note 27)
°C
°C
Maxim Integrated
3
DS28EA00
1-Wire Digital Thermometer with
Sequence Detect and PIO
ELECTRICAL CHARACTERISTICS (continued)
(T
A
= -40°C to +85°C.) (Note 1)
Note 1:
Note 2:
Note 3:
Note 4:
Specifications at T
A
= -40°C are guaranteed by design and not production tested.
System requirement.
Guaranteed by design, characterization, and/or simulation only. Not production tested.
Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system and 1-Wire recovery
times. The specified value here applies to parasitically powered systems with only one device and with the minimum
1-Wire recovery times. For more heavily loaded systems, local power or an active pullup such as that found in the
DS2482-x00, DS2480B, or DS2490 may be required. If longer t
REC
is used, higher R
PUP
values may be tolerable.
Value is 25pF maximum with local power. Maximum value represents the internal parasite capacitance when V
PUP
is first
applied. If R
PUP
= 2.2kΩ, 2.5µs after V
PUP
has been applied, the parasite capacitance does not affect normal communications.
V
TL
, V
TH
, and V
HY
are a function of the internal supply voltage, which is a function V
DD
, V
PUP
, R
PUP
, 1-Wire timing, and
capacitive loading on IO. Lower V
DD
, V
PUP
, higher R
PUP
, shorter t
REC
, and heavier capacitive loading all lead to lower val-
ues of V
TL
, V
TH
, and V
HY
.
Voltage below which, during a falling edge on IO, a logic 0 is detected.
The voltage on IO must be less than or equal to V
ILMAX
at all times when the master drives the line to a logic 0.
Voltage above which, during a rising edge on IO, a logic 1 is detected.
After V
TH
is crossed during a rising edge on IO, the voltage on IO must drop by at least V
HY
to be detected as logic 0.
The I-V characteristic is linear for voltages less than +1V.
Applies to a
single parasitically powered DS28EA00
attached to a 1-Wire line. These values also apply to networks of
multiple DS28EA00 with local supply.
The earliest recognition of a negative edge is possible at t
REH
after V
TH
has been reached on the preceding rising edge.
Defines maximum possible bit rate. Equal to 1/(t
W0LMIN
+ t
RECMIN
).
Interval during the negative edge on IO at the beginning of a presence-detect pulse between the time at which the voltage
is 80% of V
PUP
and the time at which the voltage is 20% of V
PUP
.
Interval after t
RSTL
during which a bus master is guaranteed to sample a logic 0 on IO if there is a DS28EA00 present.
Minimum limit is t
PDHMAX
+ t
FPDMAX
; the maximum limit is t
PDHMIN
+ t
PDLMIN
.
ε
in Figure 13 represents the time required for the pullup circuitry to pull the voltage on IO up from V
IL
to V
TH
. The actual
maximum duration for the master to pull the line low is t
W1LMAX
+ t
F
-
ε
and t
W0LMAX
+ t
F
-
ε,
respectively.
δ
in Figure 13 represents the time required for the pullup circuitry to pull the voltage on IO up from V
IL
to the input-high
threshold of the bus master. The actual maximum duration for the master to pull the line low is t
RLMAX
+ t
F
.
This load current is caused by the internal weak pullup, which asserts a logic 1 to the PIOB and PIOA pins. The logical
state of PIOB must not change during the execution of the Conditional Read ROM command.
Current drawn from IO during EEPROM programming or temperature conversion interval in parasite-powered mode. The
pullup circuit on IO during the programming or temperature conversion interval should be such that the voltage at IO is
greater than or equal to V
PUPMIN
. If V
PUP
in the system is close to V
PUPMIN
, then a low-impedance bypass of R
PUP
, which
can be activated during programming or temperature conversions, may need to be added. The bypass must be activated
within 10µs from the beginning of the t
PROG
or t
CONV
interval, respectively.
The t
PROG
interval begins t
REHMAX
after the trailing rising edge on IO for the last time slot of the command byte for a valid
Copy Scratchpad sequence. Interval ends once the device’s self-timed EEPROM programming cycle is complete and the
current drawn by the device has returned from I
PROG
to I
L
(parasite power) or I
DDS
(local power).
Write-cycle endurance is degraded as T
A
increases.
Not 100% production tested. Guaranteed by reliability monitor sampling.
Data retention is degraded as T
A
increases.
Guaranteed by 100% production test at elevated temperature for a shorter time; equivalence of this production test to data
sheet limit at operating temperature range is established by reliability testing.
The t
CONV
interval begins t
REHMAX
after the trailing rising edge on IO for the last time slot of the command byte for a valid
convert temperature sequence. The interval ends once the device’s self-timed temperature conversion cycle is complete
and the current drawn by the device has returned from I
CONV
to I
L
(parasite power) or I
DDS
(local power).
Drift data is preliminary and based on a 1000-hour stress test performed on another device with comparable design and
fabricated in the same manufacturing process. This test was performed at greater than +85°C with V
DD
= +5.5V.
Confirmed thermal drift results for this device are pending the completion of a new 1000-hour stress test.
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10:
Note 11:
Note 12:
Note 13:
Note 14:
Note 15:
Note 16:
Note 17:
Note 18:
Note 19:
Note 20:
Note 21:
Note 22:
Note 23:
Note 24:
Note 25:
Note 26:
Note 27:
4
Maxim Integrated
DS28EA00
1-Wire Digital Thermometer with
Sequence Detect and PIO
Pin Description
PIN
1
2, 3, 5
4
6
NAME
IO
N.C.
GND
FUNCTION
1-Wire Bus Interface and Parasitic Power Supply. Open-drain pin that requires external pullup
resistor.
No Connection
Ground Supply
Open-Drain PIOA Channel and Chain Output. For sequence detection, PIOA must be connected to
PIOA (DONE) PIOB of the next device in the chain; leave open or connect to GND for the last device in the
chain.
PIOB (EN)
V
DD
Open-Drain PIOB Channel and Chain Input. For sequence detection, PIOB of the first device in the
chain must be connected to GND.
Power Supply. Must be connected to GND for operation in parasite-power mode.
7
8
Detailed Description
The
Block Diagram
shows the relationships between
the major function blocks of the DS28EA00. The device
has three main data components: 64-bit registration
number, 64-bit scratchpad, and alarm and configura-
tion registers. The 1-Wire ROM function control unit
processes the ROM function commands that allow the
device to function in a networked environment. The
device function control unit implements the device-spe-
cific control functions, such as read/write, temperature
conversion, setting the chain state for sequence detec-
tion, and PIO access. The cyclic redundancy check
(CRC) generator assists the master verifying data
integrity when reading temperatures and memory data.
In the sequence-detect process, PIOB functions as an
input, while PIOA provides the connection to the next
device. The power-supply sensor allows the master to
remotely read whether the DS28EA00 has local power
available.
Figure 1 shows the hierarchical structure of the 1-Wire
protocol. The bus master must first provide one of the
eight ROM function commands: Read ROM, Match
ROM, Search ROM, Conditional (Alarm) Search ROM,
Conditional Read ROM, Skip ROM, Overdrive-Skip
ROM, Overdrive-Match ROM.
Upon completion of an overdrive ROM command exe-
cuted at standard speed, the device enters overdrive
mode, where all subsequent communication occurs at
a higher speed. The protocol required for these ROM
function commands is described in Figure 11. After a
ROM function command is successfully executed, the
device-specific control functions become accessible
and the master can provide any one of the nine avail-
able commands. The protocol for these control function
commands is described in Figure 9.
All data is read
and written least significant (LS) bit first.
64-Bit Registration Number
Each DS28EA00 contains a unique registration number
that is 64 bits long. The first 8 bits are a 1-Wire family
code. The next 48 bits are a unique serial number. The
last 8 bits are a CRC of the first 56 bits (see Figure 2 for
details). The 1-Wire CRC is generated using a polyno-
mial generator consisting of a shift register and XOR
gates as shown in Figure 3. The polynomial is X
8
+ X
5
+
X
4
+ 1. Additional information about the 1-Wire CRC is
available in Application Note 27:
Understanding and
Using Cyclic Redundancy Checks with Maxim iButton
®
Products.
The shift register bits are initialized to 0. Then starting
with the least significant bit of the family code, one bit
at a time is shifted in. After the eighth bit of the family
code has been entered, then the 48-bit serial number is
entered. After the last byte of the serial number has
been entered, the shift register contains the CRC value.
Shifting in the 8 bits of CRC returns the shift register to
all 0s.
iButton is a registered trademark of Maxim Integrated Products, Inc.
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