DATASHEET
ISL97686
4-Channel LED Driver with Independent Channel Control for Dynamic Dimming
The
ISL97686
is a PWM controlled LED driver that supports
4 channels of LED current for monitor and TV LCD backlight
applications. It is capable of driving 160mA per channel from a
9V to 32V input supply, with current sources rated up to 75V
absolute maximum.
The ISL97686’s current sources achieve typical current
matching to ±1%, while dynamically maintaining the
minimum required V
OUT
necessary for regulation. This adaptive
scheme compensates for the non-uniformity of forward
voltage variance in the LED strings.
The ISL97686 dimming can be controlled by a high speed SPI
interface for independent channel control for dynamic
dimming function synthesized on chip at 10-bit resolution.
The ISL97686 has an advanced dynamic headroom control
function, which monitors the highest LED forward voltage
string, and regulates the output to the correct level to minimize
power loss. This proprietary regulation scheme also allows for
extremely linear PWM dimming from 0.02% to 100%. The LED
current can also be switched between two current levels, giving
support for 3D applications. The ISL97686 incorporates
extensive protections of string open and short circuit
detections, OVP, and OTP.
FN7953
Rev.1.00
Sep 19, 2017
Features
• 4 x 160mA, 75V rated channels with integrated channel
regulation FETs
• Channels can be ganged for high current
- 2 x 350mA
- 1 x 700mA
• 9V~32V input voltage
• Dimming modes:
- Independent channel dimming control with SPI
- PWM dimming with adjustable output frequency
- 10-bit dimming resolution
- VSYNC mode
• Two selectable current levels for 3D applications
• Current matching of ±1%
• Integrated fault protection features such as string open
circuit protection, string short circuit protection, overvoltage
protection, and over-temperature protection
• 28 Ld 5x5mm TQFN and 28 Ld 300mil SOIC packages
available
Related Literature
• For a full list of related documents, visit our website
-
ISL97686
product page
Applications
• Monitor and TV LED backlighting
• General, industrial, and automotive lighting
V
IN
: 9V~32V
Fuse
D1
VIN
VDC
VLOGIC
EN
CLK
SDI
SDO
/CS
EN_VSYNC
CSEL
ISET1
ISET2
OSC
PWM_SET/PLL
CH1
CH2
CH3
CH4
OVP
SLEW
GD
CS
R
SENSE
Q1
160mA MAX PER STRING
110
100
CHANNEL CURRENT (mA)
90
80
70
60
50
40
30
20
10
0
0
20
40
60
80
100
I_CH1
I_CH4
I_CH2
I_CH3
PGND
COMP
DIMMING DUTY CYCLE (%)
FIGURE 1. ISL97686 APPLICATION DIAGRAM
FIGURE 2. PWM DIMMING LINEARITY
FN7953 Rev.1.00
Sep 19, 2017
Page 1 of 22
ISL97686
Block Diagram
V
IN
: 9V~32V
FUSE
160mA MAX PER STRING
VIN
REG1
ANALOG BIAS
DIGITAL
REG2
BIAS
FSW
EN
SLEW
O/P SHORT
FAULT/STATUS
REGISTER
GD
CS
VDC
VLOGIC
OSC
OVP
OVP
OVP
OSC &
RAMP
COMP
=0
IMAX
ILIMIT
LOGIC
FET
DRIVERS
COMP
GM
AMP
FAULT/STATUS
CONTROL
HIGHEST VF
STRING DETECT
VSET
+
-
OPEN CKT, SHORT CKT
DETECTS
CH1
CH4
1
2
3
+
-
ISET1
ISET2
CSEL
REF
GEN
REF_OVP
REF_VSC
GND
+
-
TEMP
SENSOR
4
/CS
CLK
SDI
SDO
OSC
SERIAL
INTERFACE
LED
DIMMING
CONTROLLER
PLL
EN_VSYNC
PWM_SET/PLL
FIGURE 3. ISL97686 BLOCK DIAGRAM
FN7953 Rev.1.00
Sep 19, 2017
Page 2 of 22
ISL97686
Pin Configurations
ISL97686
(28 LD 5x5 TQFN)
TOP VIEW
PGND
CSEL
CH1
CH2
PGND
CH3
CH4
ISL97686
(28 LD SOIC)
TOP VIEW
CH2
21
NC
20
OSC
19
ISET2
1
2
28
CH3
27
CH4
26
PGND
25
NC
24
OSC
23
ISET2
22
ISET1
21
COMP
20
OVP
19
PWM_SET/PLL
18
17
16
15
28
27
26
25
24
23
22
SDO
1
CS
2
CLK
3
SDI
4
VLOGIC
5
CH1
PGND
3
CSEL
SDO
CS
4
5
6
7
8
9
EXPOSED
THERMAL PAD
18
ISET1
17
COMP
16
OVP
15
PWM_SET/PLL
EN_VSYNC
6
VDC
7
8
9
10
11
12
13
14
CLK
SDI
VLOGIC
AGND
SLEW
VIN
GD
EN
PGND
CS
EN_VSYNC
10
VDC
11
VIN
12
EN
13
AGND
14
PGND
CS
SLEW
GD
Pin Descriptions
TQFN SOIC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
PIN NAME
SDO
CS
CLK
SDI
VLOGIC
EN_VSYNC
VDC
VIN
EN
AGND
GD
SLEW
CS
PGND
PWM_SET/PLL
OVP
COMP
ISET1
PIN TYPE
I
I
I
I
S
I
S
S
I
S
O
I
I
S
I
I
I
I
Serial data output to next driver
Chip select
Serial clock
Serial data input
Internal 2.5V Digital Bias Regulator. Needs Decoupling Capacitor added to ground
Frame synchronization enable. Ties high to VDC for enable V
SYNC
function. PWM_SET/PLL also needs to be
configured with an RC network. Pin can be tied to VDC or VLOGIC to enable function
Internal 5V Analog Bias Regulator. Needs Decoupling Capacitor added to ground
Main Power Input. Range: 9V to 32V
LED Driver Enable. Whole chip will shut down when low
Analog Ground
External Boost FET gate control
Boost Regulation Switching Slew Rate control
External Boost FET current sense input
Boost FET gate driver power ground and ground reference for CS pin
For direct PWM mode, tie this pin high to VDC. For other non-VSYNC modes, connect to a resistor to set the
dimming frequency. If the VSYNC function is enabled, connect this pin to the PLL loop filter network.
Overvoltage Protection Input as well as Output Voltage feedback pin
Boost compensation
Resistor connection for setting LED current. 28.7kΩ= 100mA
PIN DESCRIPTION
FN7953 Rev.1.00
Sep 19, 2017
Page 3 of 22
ISL97686
Pin Descriptions
(Continued)
TQFN SOIC
19
20
21
22
23
24
25
26
27
28
23
24
25
26
27
28
1
2
3
4
PIN NAME
ISET2
OSC
NC
PGND
CH4
CH3
CH2
CH1
PGND
CSEL
S
I
I
I
I
S
I
PIN TYPE
I
I
PIN DESCRIPTION
Resistor connection for setting LED current. 28.7kΩ= 100mA
Boost switching frequency adjustment
No connection
Power Ground return for LED current
LED PWM Driver
LED PWM Driver
LED PWM Driver
LED PWM Driver
Power Ground return for LED current
ISET Resistor Selection Pin.
CSEL = 0 : ISET 1 resistor sets LED current
CSEL = 1 : ISET 2 resistor sets LED current
Ordering Information
PART NUMBER
(Notes
3, 4)
ISL97686IRTZ (Note
1)
ISL97686IBZ (Note
2)
ISL97686IBZ-EVAL1Z
NOTES:
1. Add “-T” suffix for 6k unit tape and reel. Refer to
TB347
for details on reel specifications.
2. Add “-TK” suffix for 1k unit tape and reel. Refer to
TB347
for details on reel specifications.
3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
4. For Moisture Sensitivity Level (MSL), see the product information page for
ISL97686.
For more information on MSL, see
TB363.
PART
MARKING
ISL9768 6IRTZ
ISL97686IBZ
PACKAGE
(RoHS COMPLIANT)
28 Ld 5x5 TQFN
28 Ld SOIC (300mil)
L28.5x5B
M28.3
PKG.
DWG. #
Evaluation Board (None of LEDs on the evaluation board)
FN7953 Rev.1.00
Sep 19, 2017
Page 4 of 22
ISL97686
Absolute Maximum Ratings
(T
A
= +25°C)
Thermal Information
Thermal Resistance
JA
(°C/W)
28 Ld TQFN (4 layer + vias, Notes
5, 7)
. . .
32
28 Ld SOIC (4 layer, Notes
6, 8)
. . . . . . . . .
54
Thermal Characterization (Typical, Note
9)
JC
(°C/W)
4
25
PSI
JT
(°C/W)
VIN, EN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 45V
VDC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 5.75V
VLOGIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.75V
COMP, ISET1, ISET2, PWM_SET,
OSC, CS, OVP. . . . . . . . . . . . . . . . . . . . . . .-0.3V to min (VDC+0.3V, 5.75V)
EN_VSYNC, CSEL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 5.75V
CLK, SDI, SDO, CS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 5.75V
CH1 - CH4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 75V
GD, SLEW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 18V
PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V
Above voltage ratings are all with respect to AGND pin
ESD Rating
Human Body Model (Tested per JESD22-A114F) . . . . . . . . . . . . . . . . 2kV
Machine Model (Tested per JESD22-A115C) . . . . . . . . . . . . . . . . . . 200V
Charged Device Model (JESD22-C101E) . . . . . . . . . . . . . . . . . . . . . . . 1kV
Latch Up (Tested per JESD-78B; Class 2, Level A) . . . . . . . . . . . . . . 100mA
28 Ld TQFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1
28 Ld SOIC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4
Maximum Continuous Junction Temperature . . . . . . . . . . . . . . . . .+125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Power Dissipation
TQFN (W)
SOIC (W)
T
A
< +25°C . . . . . . . . . . . . . . . . . . . . . . . . . .
3.13
1.85
T
A
< +70°C . . . . . . . . . . . . . . . . . . . . . . . . . .
1.72
1.02
T
A
< +85°C . . . . . . . . . . . . . . . . . . . . . . . . . .
1.25
0.74
T
A
< +105°C . . . . . . . . . . . . . . . . . . . . . . . .
0.63
0.37
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Refer to
TB493
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +105°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
5.
JA
is measured in free air with the component mounted on a high-effective thermal conductivity test board with “direct attach” features. See
TB379.
6.
JA
is measured with the component mounted on a high effective thermal conductivity test board in free air. See
TB379
for details.
7. For
JC
, the “case temp” location is the center of the exposed metal pad on the package underside.
8. For
JC
, the “case temp” location is taken at the package top center.
9. PSI
JT
is the PSI junction-to-top thermal characterization parameter. If the package top temperature can be measured with this rating then the die
junction temperature can be estimated more accurately than the
JC
and
JC
thermal resistance ratings.
Electrical Specifications
All specifications below are characterized at T
A
= -40°C to +105°C; V
IN
= 12V, EN = 5V. Boldface limits apply
over the operating temperature range, -40°C to +105°C.
PARAMETER
DESCRIPTION
Backlight Supply Voltage
VIN Shutdown Current
Switching
(Note
11)
EN = 0
R
FPWM
= 3.3kΩ,
I
LED
= 100mA,
f
SW
= 600kHz,
C
OUT_SW
= 1nF
2.9
300
V
IN
> 6V
I
VDC
= 30mA
V
IN
> 6V
I
VLOGIC
= 30mA
2.3
4.8
5
71
2.4
31
16
R
SENSE
= 50mΩ
C
OUT_SW
= 1000pF
C
OUT_SW
= 1000pF
C
OUT_SW
= 1000pF
3.1
3.4
20
17.6
10
3.8
5.1
100
2.5
100
10
CONDITION
MIN
(Note
10)
9
TYP
MAX
(Note
10)
UNIT
32
5
13
V
µA
mA
GENERAL
V
IN
I
VIN_STBY
I
VIN_ACTIVE
Non-switching
V
UVLO
V
UVLO_HYS
V
DC
V
DC_DROP
V
LOGIC
V
LOGIC_DROP
t
SS
I
SW_LIMIT
t
R
t
F
V
GD
Undervoltage Lock-out Threshold
Undervoltage Lock-out Hysteresis
5V Analog Bias Regulator
V
DC
LDO Load Regulation Tolerance
2.5V Logic Bias Regulator
V
LOGIC
LDO Load Regulation Tolerance
Soft-Start
Boost FET Current Limit
Gate Rise Time
Gate Falling Time
Gate Driver Output Voltage
4
5.5
3.3
mA
V
mV
V
mV
V
mV
ms
A
ns
ns
V
LINEAR REGULATOR
BOOST SWITCH CONTROLLER
FN7953 Rev.1.00
Sep 19, 2017
Page 5 of 22
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