Data Sheet
April 2001
Quad Differential Receivers
BRF1A, BRF2A, BRS2B, BRR1A, and BRT1A
Features
s
Pin equivalent to the general-trade 26LS32 device,
with improved speed, reduced power consumption,
and significantly lower levels of EMI
High input impedance approximately 8 kΩ
Four line receivers per package
400 Mbits/s maximum data rate when used with
Agere Systems Inc. data transmission drivers
Meets enhanced small device interface (ESDI)
standards
4.0 ns maximum propagation delay
<0.20 V input sensitivity
−1.2
V to
+7.2
V common-mode range
−40 °C
to
+125 °C
ambient operating temperature
range (wider than the 41 Series)
Single 5.0 V
±
10% supply
Output defaults to logic 1 when inputs are left
open*
Available in four package types
Lower power requirement than the 41 Series
The BRF1A device is the generic receiver in this
family and requires the user to supply external
resistors on the circuit board for impedance
matching.
The BRF2A is identical to the BRF1A, but has an
electrostatic discharge (ESD) protection circuit
added to significantly improve the ESD human-body
model (HBM) characteristics on the differential input
terminals.
The BRS2B is identical to the BRF2A, but has a
preferred state feature that places the output in the
high state when the inputs are open, shorted to
ground, or shorted to the power supply.
The BRR1A is equivalent to the BRF1A, but has a
110
Ω
resistor connected across the differential
inputs. This eliminates the need for an external
resistor when terminating a 100
Ω
impedance line.
This device is designed to work with the DP1A or
PNPA in point-to-point applications.
The BRT1A is equivalent to the BRF1A; however, it
is provided with a Y-type resistor network across the
differential inputs and terminated to ground. The
Y-type termination provides the best EMI results.
This device is not recommended for applications
where the differences in ground voltage between the
driver and the receiver exceed 1 V. This device is
designed to work with the DG1A or PNGA in point-to-
point applications.
The powerdown loading characteristics of the
receiver input circuit are approximately 8 kΩ relative
to the power supplies; hence, they will not load the
transmission line when the circuit is powered down.
For those circuits with termination resistors, the line
will remain impedance matched when the circuit is
powered down.
The packaging options that are available for these
quad differential line drivers include a 16-pin DIP; a
16-pin, J-lead SOJ; a 16-pin, gull-wing small-outline
integrated circuit (SOIC); and a 16-pin, narrow-body,
gull-wing SOIC.
s
s
s
s
s
s
s
s
s
s
s
s
Description
These quad differential receivers accept digital data
over balanced transmission lines. They translate
differential input logic levels to TTL output logic
levels. All devices in this family have four receivers
with a common enable control. These receivers are
pin equivalent to the general-trade 26LS32, but offer
increased speed and decreased power consumption.
They replace the Agere 41 Series receivers.
* This feature is available on BRF1A and BRF2A.
Quad Differential Receivers
BRF1A, BRF2A, BRS2B, BRR1A, and BRT1A
Data Sheet
April 2001
Pin Information
AI
AI
AO
E1
BO
BI
BI
GND
1
A
2
3
4
5
6
7
8
BRF1A
BRF2A
BRS2B
B
C
D
16 V
CC
15 DI
14 DI
13 DO
12 E2
11 CO
10 CI
9
CI
AI
AI
AO
E1
BO
BI
BI
GND
1
A
2
3
4
5
6
7
8
BRR1A
B
C
D
16 V
CC
15 DI
14 DI
13 DO
12 E2
11 CO
10 CI
9
CI
AI
AI
AO
E1
BO
BI
BI
GND
1
2
3
4
5
6
7
8
BRT1A
B
C
A
D
16 V
CC
15 DI
14 DI
13 DO
12 E2
11 CO
10 CI
9
CI
12-2281.a(F)
Figure 1. Quad Differential Receiver Logic Diagrams
Table 1. Enable Truth Table
E1
0
1
0
1
E2
0
0
1
1
Condition
Active
Active
Disabled
Active
Absolute Maximum Ratings
Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are
absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in
excess of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for
extended periods can adversely affect device reliability.
Parameter
Power Supply Voltage
Ambient Operating Temperature
Storage Temperature
Symbol
V
CC
T
A
T
stg
Min
—
−40
−40
Max
6.5
125
150
Unit
V
°C
°C
Electrical Characteristics
For electrical characteristics over the temperature range, see Figure 7 through Figure 10.
Table 2. Power Supply Current Characteristics
See Figure 7 for variation in I
CC
over the temperature range. T
A
= –40 °C to +125 °C, V
CC
= 5 V
±
0.5 V.
Parameter
Power Supply Current (V
CC
= 5.5 V):
All Outputs Disabled
All Outputs Enabled
2
Symbol
I
CC
I
CC
Min
Typ
30
20
Max
45
32
Unit
mA
mA
Agere Systems Inc.
Data Sheet
April 2001
Quad Differential Receivers
BRF1A, BRF2A, BRS2B, BRR1A, and BRT1A
Electrical Characteristics
(continued)
Table 3. Voltage and Current Characteristics
For variation in minimum V
OH
and maximum V
OL
over the temperature range, see Figure 8. T
A
= –40 °C to +125 °C.
Parameter
Output Voltages, V
CC
= 4.5 V:
Low, I
OL
= 8.0 mA
High, I
OH
=
−400
µA
Enable Input Voltages:
Low, V
CC
= 5.5 V
High, V
CC
= 5.5 V
Clamp, V
CC
= 4.5 V, I
I
= –5.0 mA
Differential Input Voltages, V
IH –
V
IL
:
2
−0.80
V < V
IH
< 7.2 V,
−1.2
V < V
IL
< 6.8 V
Input Offset Voltage
Input Offset Voltage BRS2B
Output Currents, V
CC
= 5.5 V:
Off-state (high Z), V
O
= 0.4 V
Off-state (high Z), V
O
= 2.4 V
Short Circuit
Enable Currents, V
CC
= 5.5 V:
Low, V
IN
= 0.4 V
High, V
IN
= 2.7 V
Reverse, V
IN
= 5.5 V
Differential Input Currents, V
CC
= 5.5 V:
Low, V
IN
= –1.2 V
High, V
IN
= 7.2 V
Differential Input Impedance (BRR1A):
Connected Between RI and RI
Differential Input Impedance (BRT1A)
4
R
O
R
1
R
2
—
—
—
110
60
90
—
—
—
Ω
Ω
Ω
I
IL
I
IH
—
—
—
—
−1.0
1.0
mA
mA
I
IL
I
IH
I
IH
—
—
—
—
—
—
–400
20
100
µA
µA
µA
I
OZL
I
OZH
I
OS
3
—
—
–25
—
—
—
–20
20
–100
µA
µA
mA
V
TH
1
V
OFF
V
OFF
—
0.1
0.02
0.1
0.20
0.05
0.15
V
V
V
V
IL
1
V
IH
1
V
IK
—
2.0
—
—
—
—
0.7
—
–1.0
V
V
V
V
OL
V
OH
—
2.4
—
—
0.5
—
V
V
Sym
Min
Typ
Max
Unit
1. The input levels and difference voltage provide zero noise immunity and should be tested only in a static, noise-free environment.
2. Outputs of unused receivers assume a logic 1 level when the inputs are left open. (It is recommended that all unused positive inputs
be tied to the positive power supply. No external series resistor is required.)
3. Test must be performed one lead at a time to prevent damage to the device.
4. See Figure 2.
R1
RI
R1
RI
R2
12-2819.a(F)
Figure 2. BRT1A Terminating Resistor Configuration
Agere Systems Inc.
3
Quad Differential Receivers
BRF1A, BRF2A, BRS2B, BRR1A, and BRT1A
Data Sheet
April 2001
Timing Characteristics
Table 4. Timing Characteristics
(See Figure 4 and Figure 5.)
For propagation delays (t
PLH
and t
PHL
) over the temperature range, see Figure 9 and Figure 10.
Propagation delay test circuit connected to output is shown in Figure 6.
T
A
= –40 °C to +125 °C, V
CC
= 5 V
±
0.5 V.
Parameter
Symbol
Min
1.5
1.5
—
—
—
—
—
—
—
—
—
—
—
Typ
2.5
2.5
5
5
—
—
0.8
—
—
8
8
—
—
Max
4.0
4.0
12
12
0.7
4.0
1.4
1.5
0.3
12
12
3.0
3.0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Propagation Delay:
Input to Output High
t
PLH
Input to Output Low
t
PHL
Disable Time, C
L
= 5 pF:
High-to-high Impedance
t
PHZ
Low-to-high Impedance
t
PLZ
Pulse Width Distortion, ltpHL
−
tpLHI:
Load Capacitance (C
L
) = 15 pF
tskew1
Load Capacitance (C
L
) = 150 pF
tskew1
Output Waveform Skews:
Part-to-Part Skew, T
A
= 75 °C
∆tskew1p-p
Part-to-Part Skew, T
A
= –40 °C to +125 °C
∆tskew1p-p
Same Part Skew
∆tskew
Enable Time:
High Impedance to High
t
PZH
High Impedance to Low
t
PZL
Rise Time (20%—80%)
t
tLH
Fall Time (80%—20%)
t
tHL
EXTRINSIC PROPAGATION DELAY, t
P
(ns)
7
6
5
4
t
PLH
(TYP)
3
2
t
PHL
(TYP)
1
0
0
25
50
75
100
125
150
175 200
LOAD CAPACITANCE, C
L
(pF)
12-3462(F)
Note: This graph is included as an aid to the system designers. Total circuit delay varies with load capacitance. The total delay is the sum of the
delay due to the external capacitance and the intrinsic delay of the device.
Figure 3. Typical Extrinsic Propagation Delay vs. Load Capacitance at 25 °C
4
Agere Systems Inc.
Data Sheet
April 2001
Quad Differential Receivers
BRF1A, BRF2A, BRS2B, BRR1A, and BRT1A
Timing Characteristics
(continued)
INPUT
INPUT
3.7 V
3.2 V
2.7 V
t
PHL
OUTPUT
80%
20%
t
tHL
20%
t
PLH
80%
V
OH
1.5 V
V
OL
t
tLH
12-2251.b(F)
Figure 4. Receiver Propagation Delay Timing
3V
E1*
1.5 V
0V
3V
E2
†
1.5 V
0V
t
PHZ
t
PZH
t
PLZ
t
PZL
V
OH
OUTPUT
V
OL
∆V
= 0.5 V
∆V
= 0.5 V
∆V
= 0.5 V
∆V
= 0.5 V
12-253.b(F)
* E2 = 1 while E1 changes state.
† E1 = 0 while E2 changes state.
Figure 5. Receiver Enable and Disable Timing
Test Conditions
Parametric values specified under the Electrical Characteristics and Timing Characteristics sections for the data
transmission driver devices are measured with the following output load circuits.
5V
TO OUTPUT OF
DEVICE UNDER
TEST
C
L
15 pF*
5 kΩ
2 kΩ
12-2249(F)
* Includes probe and jig capacitances.
Note: All 458E, IN4148, or equivalent diodes.
Figure 6. Receiver Propagation Delay Test Circuit
Agere Systems Inc.
5
FPGA/CPLD
京公网安备 11010802033920号
EEWORLD
