Data Sheet
March 1999
Quad Differential Receivers
BRF1A, BRF2A, BRR1A, BRS2A, and BRT1A
Features
s
Pin equivalent to the general-trade 26LS32 device,
with improved speed, reduced power consumption,
and significantly lower levels of EMI
High input impedance
≅
8 kΩ
Four line receivers per package
400 Mbits/s maximum data rate when used with
Lucent Technologies Microelectronics Group data
transmission drivers
Meets ESDI standards
4.0 ns maximum propagation delay
<0.20 V input sensitivity
−1.2
V to
+7.2
V common-mode range
−40 °C
to
+125 °C
ambient operating temperature
range (wider than the 41 Series)
Single 5.0 V
±
10% supply
Output defaults to logic 1 when inputs are left
open*
Available in four package types
Lower power requirement than the 41 Series
The BRF1A device is the generic receiver in this fam-
ily and requires the user to supply external resistors
on the circuit board for impedance matching.
The BRF2A is identical to the BRF1A but has an
ESD protection circuit added to significantly improve
the ESD (HBM) characteristics on the differential
input terminals.
The BRS2A is identical to the BRF2A but has a pre-
ferred state feature that places the output in the high
state when the inputs are open, shorted to ground, or
shorted to the power supply.
The BRR1A is equivalent to the BRF1A, but has a
110
Ω
resistor connected across the differential
inputs. This eliminates the need for an external resis-
tor when terminating a 100
Ω
impedance line. This
device is designed to work with the BDP1A or
BPNPA in point-to-point applications.
The BRT1A is equivalent to the BRF1A; however, it is
provided with a Y-type resistor network across the dif-
ferential inputs and terminated to ground. The Y-type
termination provides the best EMI results. This
device is not recommended for applications where
the differences in ground voltage between the driver
and the receiver exceed 1 V. This device is designed
to work with the BDG1A or BPNGA in point-to-point
applications.
The powerdown loading characteristics of the
receiver input circuit are approximately 8 kΩ relative
to the power supplies; hence, they will not load the
transmission line when the circuit is powered down.
For those circuits with termination resistors, the line
will remain impedance matched when the circuit is
powered down.
The packaging options that are available for these
quad differential line drivers include a 16-pin DIP; a
16-pin, J-lead SOJ; a 16-pin, gull-wing SOIC; and a
16-pin, narrow-body, gull-wing SOIC.
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Description
These quad differential receivers accept digital data
over balanced transmission lines. They translate dif-
ferential input logic levels to TTL output logic levels.
All devices in this family have four receivers with a
common enable control. These receivers are pin
equivalent to the general-trade 26LS32, but offer
increased speed and decreased power consumption.
They replace the Lucent 41 Series receivers.
* This feature is available on BRF1A and BRF2A.
Quad Differential Receivers
BRF1A, BRF2A, BRR1A, BRS2A, and BRT1A
Data Sheet
March 1999
Pin Information
AI
AI
AO
E1
BO
BI
BI
GND
1
A
2
3
4
5
6
7
8
BRF1A
BRF2A
B
C
D
16 V
CC
15 DI
14 DI
13 DO
12 E2
11 CO
10 CI
9
CI
AI
AI
AO
E1
BO
BI
BI
GND
1
A
2
3
4
5
6
7
8
BRR1A
B
C
D
16 V
CC
15 DI
14 DI
13 DO
12 E2
11 CO
10 CI
9
CI
AI
AI
AO
E1
BO
BI
BI
GND
1
2
3
4
5
6
7
8
BRT1A
B
C
A
D
16 V
CC
15 DI
14 DI
13 DO
12 E2
11 CO
10 CI
9
CI
12-2281aC
Figure 1. Quad Differential Receiver Logic Diagrams
Table 1. Enable Truth Table
E1
0
1
0
1
E2
0
0
1
1
Condition
Active
Active
Disabled
Active
Absolute Maximum Ratings
Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are abso-
lute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess
of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for extended
periods can adversely affect device reliability.
Parameter
Power Supply Voltage
Ambient Operating Temperature
Storage Temperature
Symbol
V
CC
T
A
T
stg
Min
—
−40
−55
Max
6.5
125
150
Unit
V
°C
°C
Electrical Characteristics
For electrical characteristics over the temperature range, see Figures 7 through 10.
Table 2. Power Supply Current Characteristics
See Figure 7 for variation in I
CC
over the temperature range. T
A
= –40 °C to +125 °C, V
CC
= 5 V
±
0.5 V.
Parameter
Power Supply Current (V
CC
= 5.5 V):
All Outputs Disabled
All Outputs Enabled
2
Symbol
I
CC
I
CC
Min
Typ
30
20
Max
45
32
Unit
mA
mA
Lucent Technologies Inc.
Data Sheet
March 1999
Quad Differential Receivers
BRF1A, BRF2A, BRR1A, BRS2A, and BRT1A
Electrical Characteristics
(continued)
Table 3. Voltage and Current Characteristics
For variation in minimum V
OH
and maximum V
OL
over the temperature range, see Figure 8. T
A
= –40 °C to +125 °C.
Parameter
Output Voltages, V
CC
= 4.5 V:
Low, I
OL
= 8.0 mA
High, I
OH
=
−400 µA
Enable Input Voltages:
Low, V
CC
= 5.5 V
High, V
CC
= 5.5 V
Clamp, V
CC
= 4.5 V, I
I
= –5.0 mA
Differential Input Voltages, V
IH –
V
IL
:
†
−0.80
V < V
IH
< 7.2 V,
−1.2
V < V
IL
< 6.8 V
Input Offset Voltage
Input Offset Voltage BRS2A
Output Currents, V
CC
= 5.5 V:
Off-state (high Z), V
O
= 0.4 V
Off-state (high Z), V
O
= 2.4 V
Short Circuit
Enable Currents, V
CC
= 5.5 V:
Low, V
IN
= 0.4 V
High, V
IN
= 2.7 V
Reverse, V
IN
= 5.5 V
Differential Input Currents, V
CC
= 5.5 V:
Low, V
IN
= –1.2 V
High, V
IN
= 7.2 V
Differential Input Impedance (BRR1A):
Connected Between RI and RI
Differential Input Impedance (BRT1A)
§
Sym
V
OL
V
OH
V
IL
*
V
IH
*
V
IK
V
TH
*
V
OFF
V
OFF
I
OZL
I
OZH
I
OS‡
I
IL
I
IH
I
IH
I
IL
I
IH
R
O
R
1
R
2
Min
—
2.4
—
2.0
—
—
—
—
–25
—
—
—
—
—
—
—
—
Typ
—
—
—
—
—
0.1
0.02
0.1
—
—
—
—
—
—
—
—
110
60
90
Max
0.5
—
0.7
—
–1.0
0.20
0.05
0.15
–20
20
–100
–400
20
100
−1.0
1.0
—
—
—
Unit
V
V
V
V
V
V
V
µA
µA
mA
µA
µA
µA
mA
mA
Ω
Ω
Ω
* The input levels and difference voltage provide zero noise immunity and should be tested only in a static, noise-free environment.
† Outputs of unused receivers assume a logic 1 level when the inputs are left open. (It is recommended that all unused positive inputs
be tied to the positive power supply. No external series resistor is required.)
‡ Test must be performed one lead at a time to prevent damage to the device.
§ See Figure 2.
R1
RI
R2
R1
RI
12-2819AF
Figure 2. BRT1A Terminating Resistor Configuration
Lucent Technologies Inc.
3
Quad Differential Receivers
BRF1A, BRF2A, BRR1A, BRS2A, and BRT1A
Data Sheet
March 1999
Timing Characteristics
Table 4. Timing Characteristics
(See Figures 4 and 5.)
For propagation delays (t
PLH
and t
PHL
) over the temperature range, see Figures 9 and 10.
Propagation delay test circuit connected to output is shown in Figure 6.
T
A
= –40 °C to +125 °C, V
CC
= 5 V
±
0.5 V.
Parameter
Symbol
Propagation Delay:
Input to Output High
t
PLH
Input to Output Low
t
PHL
Disable Time, C
L
= 5 pF:
High-to-high Impedance
t
PHZ
Low-to-high Impedance
t
PLZ
Pulse Width Distortion, ltpHL
−
tpLHI:
Load Capacitance (C
L
) = 15 pF
tskew1
Load Capacitance (C
L
) = 150 pF
tskew1
Output Waveform Skews:
Part-to-Part Skew, T
A
= 75 °C
∆tskew1p-p
Part-to-Part Skew, T
A
= –40 °C to +125 °C
∆tskew1p-p
Same Part Skew
∆tskew
Enable Time:
High Impedance to High
t
PZH
High Impedance to Low
t
PZL
Rise Time (20%—80%)
t
tLH
Fall Time (80%—20%)
t
tHL
Min
1.5
1.5
—
—
—
—
—
—
—
—
—
—
—
Typ
2.5
2.5
5
5
—
—
0.8
—
—
8
8
—
—
Max
4.0
4.0
12
12
0.7
4.0
1.4
1.5
0.3
12
12
3.0
3.0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
EXTRINSIC PROPAGATION DELAY, t
P
(ns)
7
6
5
4
t
PLH
(TYP)
3
2
t
PHL
(TYP)
1
0
0
25
50
75
100
125
150
175 200
LOAD CAPACITANCE, C
L
(pF)
12-3462F
Note: This graph is included as an aid to the system designers. Total circuit delay varies with load capacitance. The total delay is the sum of
the delay due to the external capacitance and the intrinsic delay of the device.
Figure 3. Typical Extrinsic Propagation Delay Versus Load Capacitance at 25 °C
4
Lucent Technologies Inc.
Data Sheet
March 1999
Quad Differential Receivers
BRF1A, BRF2A, BRR1A, BRS2A, and BRT1A
Timing Characteristics
(continued)
INPUT
INPUT
3.7 V
3.2 V
2.7 V
t
PHL
OUTPUT
80%
20%
t
tHL
20%
t
PLH
80%
V
OH
1.3 V
V
OL
t
tLH
12-2251aF
Figure 4. Receiver Propagation Delay Timing
3V
E1*
1.3 V
0V
3V
E2
†
t
PHZ
t
PZH
t
PLZ
t
PZL
1.3 V
0V
V
OH
OUTPUT
V
OL
∆V
= 0.5 V
1.3 V
∆V
= 0.5 V
∆V
= 0.5 V
∆V
= 0.5 V
12-2538aF
* E2 = 1 while E1 changes state.
† E1 = 0 while E2 changes state.
Figure 5. Receiver Enable and Disable Timing
Test Conditions
Parametric values specified under the Electrical Characteristics and Timing Characteristics sections for the data
transmission driver devices are measured with the following output load circuits>
+5 V
TO OUTPUT OF
DEVICE UNDER
TEST
C
L
15 pF*
5 kΩ
2 kΩ
12-2249F
*Includes probe and jig capacitances.
Note: All 458E, IN4148, or equivalent diodes.
Figure 6. Receiver Propagation Delay Test Circuit
Lucent Technologies Inc.
5
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