A5988
Quad DMOS Full-Bridge PWM Motor Driver
FEATURES AND BENEFITS
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40 V output rating
4 full bridges
Dual stepper motor driver
High-current outputs
3.3 and 5 V compatible logic
Synchronous rectification
Internal undervoltage lockout (UVLO)
Thermal shutdown circuitry
Crossover-current protection
Overcurrent protection
Low-power sleep mode
Low-profile QFN package
The A5988 is a quad DMOS full-bridge driver capable of driving
up to two stepper motors or four DC motors. Each full-bridge
output is rated up to 1.6 A and 40 V. The A5988 includes fixed
off-time pulse-width modulation (PWM) current regulators,
along with 2- bit nonlinear DACs (digital-to-analog converters)
that allow stepper motors to be controlled in full, half, and
quarter steps, and DC motors in forward, reverse, and coast
modes. The PWM current regulator uses the Allegro
™
patented
mixed decay mode for reduced audible motor noise, increased
step accuracy, and reduced power dissipation.
Internal synchronous rectification control circuitry is provided
to improve power dissipation during PWM operation.
Protection features include thermal shutdown with hysteresis,
undervoltage lockout (UVLO) and crossover-current protection.
Special power-up sequencing is not required.
The A5988 is supplied in two packages, EV and JP, with exposed
power tabs for enhanced thermal performance. The EV is a
6 mm × 6 mm, 36-pin QFN package with a nominal overall
package height of 0.90 mm. The JP is a 7 mm × 7 mm 48-pin
LQFP. Both packages are lead (Pb) free, with 100% matte-tin
leadframe plating.
DESCRIPTION
PACKAGES
Package EV, 36-pin QFN
0.90 mm nominal height
with exposed thermal pad
Package JP, 48-pin LQFP
with exposed thermal pad
Not to scale
0.1 µF
50 V
0.1 µF
50 V
V
MOTOR
32 V
100 µF
50 V
0.22 µF
50 V
VBB1
* JP package only
FAULTn*
PHASE1
I01
I11
PHASE2
I02
Microprocessor
I12
PHASE3
I03
I13
PHASE4
I04
I14
VREF1
V
REF
VREF2
VREF3
VREF4
SLEEPn
VBB2
OUT1A
OUT1B
OUT2A
OUT2B
OUT3A
VCP
CP1
CP2
Bipolar Stepper Motors
A5988
OUT3B
OUT4A
OUT4B
SENSE2
SENSE1
SENSE3
SENSE4
R
S2
R
S1
R
S3
R
S4
Figure 1: Typical Application Circuit
A5988-DS, Rev. 1
A5988
SELECTION GUIDE
Part Number
A5988GEVTR-T
A5988GJPTR-T
A5988GEVTR-1-T
A5988GJPTR-1-T
Quad DMOS Full-Bridge PWM Motor Driver
Package
36-pin QFN with exposed thermal pad
48-pin LQFP with exposed thermal pad
36-pin QFN with exposed thermal pad
48-pin LQFP with exposed thermal pad
Packing
1500 pieces per reel
1500 pieces per reel
1500 pieces per reel
1500 pieces per reel
Fixed Off-Time (µs)
30
30
8.1
8.1
ABSOLUTE MAXIMUM RATINGS
Characteristic
Load Supply Voltage
Output Current
Symbol
V
BB
I
OUT
May be limited by duty cycle, ambient temperature, and heat sinking. Under
any set of conditions, do not exceed the specified current rating or a Junction
Temperature of 150°C.
Notes
Rating
–0.5 to 40
1.6
Units
V
A
Logic Input Voltage Range
SENSEx Pin Voltage
VREFx Pin Voltage
Operating Temperature Range
Junction Temperature
Storage Temperature Range
V
IN
V
SENSEx
Pulsed t
w
< 1 µs
V
REFx
T
A
T
J
(max)
T
stg
Range G
–0.3 to 7
0.5
2.5
2.5
–40 to 105
150
–40 to 125
V
V
V
V
ºC
ºC
ºC
THERMAL CHARACTERISTICS (may require derating at maximum conditions)
Characteristic
Package Thermal Resistance
Symbol
R
θJA
Test Conditions
EV package, 4-layer PCB based on JEDEC standard
JP package, 4-layer PCB based on JEDEC standard
Min.
27
23
Units
ºC/W
ºC/W
Power Dissipation versus Ambient Temperature
5500
5000
4500
4000
JP Package
4-layer PCB
(R
θJA
= 23 ºC/W)
Power Dissipation, P
D
(mW)
3500
3000
2500
2000
1500
1000
500
0
25
50
75
100
125
Temperature (°C)
150
175
EV Package
4-layer PCB
(R
θJA
= 27 ºC/W)
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
2
A5988
Quad DMOS Full-Bridge PWM Motor Driver
FUNCTIONAL BLOCK DIAGRAM
0.1 µF
50 V
0.1 µF
50 V
100 µF
50 V
0.22 µF
50 V
To
V
BB2
*JP
package
only
FAULTn*
VBB1
VCP
CP1
CP2
OCP
V
REG
V
CP
SLEEPn
DMOS
FULL-BRIDGE 1
OSC
CHARGE PUMP
OUT1A
PHASE1
I01
I11
PHASE2
I02
I12
Sense1
VREF1
3
GATE
DRIVE
OUT1B
CONTROL LOGIC
BRIDGES 1 AND 2
SENSE1
DMOS
FULL-BRIDGE 2
-
+
PWM LATCH
BLANKING
OUT2A
VREF2
3
Sense2
+
-
PWM LATCH
BLANKING
OUT2B
PHASE3
I03
I13
PHASE4
I04
I14
GATE
DRIVE
Sense3
VBB2
V
REG
V
CP
Sense2
CONTROL LOGIC
BRIDGES 3 AND 4
SENSE2
VBB2
DMOS
FULL-BRIDGE 3
OUT3A
OUT3B
SENSE3
Sense3
VREF3
3
-
+
PWM LATCH
BLANKING
DMOS
FULL-BRIDGE 4
VREF4
3
Sense4
OUT4A
OUT4B
PGND
GND
+
-
PWM LATCH
BLANKING
Sense4
SENSE4
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
3
A5988
Quad DMOS Full-Bridge PWM Motor Driver
ELECTRICAL CHARACTERISTICS
1
: Valid at T
A
= 25°C, V
BB
= 40 V, unless otherwise noted
Characteristics
Load Supply Voltage Range
Output On Resistance
V
f
, Outputs
Output Leakage
I
DSS
Symbol
V
BB
R
DS(on)
Operating
Source driver, I
OUT
= –1.2 A, T
J
= 25°C
Sink driver, I
OUT
= 1.2 A, T
J
= 25°C
I
OUT
= 1.2 A
Outputs, V
OUT
= 0 to V
BB
I
OUT
= 0 mA, outputs on, PWM = 50 kHz,
DC = 50%
Outputs off
Sleep mode
Output Driver Slew Rate
CONTROL LOGIC
Logic Input Voltage
Logic Input Current
Logic Input Hysteresis
Sleep Rising Threshold
Sleep Falling Threshold
Sleep Hysteresis
Sleep Input Current
Crossover Delay
Blank Time
VREFx Pin Input Voltage Range
VREFx Pin Reference Input Current
Current Trip-Level Error
3
PROTECTION CIRCUITS
VBB UVLO Threshold
VBB Hysteresis
Overcurrent Protection Threshold
Fault Output Voltage
Fault Output Leakage Current
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis
1
For
2
Typical
Test Conditions
Min.
8
–
–
–
–20
–
–
–10
50
2
–
Typ.
2
–
500
500
–
–
–
13.7
<1
100
–
–
<1
300
2.7
2.4
325
100
425
1
–
–
–
–
–
7.6
500
–
–
–
165
15
Max.
40
600
600
1.2
20
23
16
10
150
–
0.8
20
500
2.95
–
450
150
1000
1.3
1.5
±1
5
5
15
7.9
600
–
0.5
1
175
–
Units
V
mΩ
mΩ
V
µA
mA
mA
µA
ns
V
V
µA
mV
V
V
mV
µA
ns
µs
V
μA
%
%
%
V
mV
A
V
µA
°C
°C
VBB Supply Current
I
BB
SR
OUT
V
IN(1)
V
IN(0)
I
IN
V
hys
10% to 90%
V
IN
= 0 to 5 V
–20
150
2.5
–
250
–
t
COD
t
BLANK
V
REFx
I
REF
V
ERR
Operating
V
REF
= 1.5
V
REF
= 1.5, phase current = 100%
V
REF
= 1.5, phase current = 67%
V
REF
= 1.5, phase current = 33%
V
UV(VBB)
V
UV(VBB)hys
I
OUT
= 1 mA
No fault, V
OUT
= 5 V
T
JTSD
T
JTSDhys
V
BB
rising
250
0.7
0.0
–
–5
–5
–15
7.3
400
1.6
–
–
155
–
input and output current specifications, negative current is defined as coming out of (sourcing) the specified device pin.
data are for initial design estimations only, and assume optimum manufacturing and application conditions. Performance may vary for indi-
vidual units, within the specified maximum and minimum limits.
3
V
ERR
= [(V
REF
/3) – V
SENSE
] / (V
REF
/3).
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
4
A5988
Quad DMOS Full-Bridge PWM Motor Driver
FUNCTIONAL DESCRIPTION
Device Operation.
The A5988 is designed to operate two
stepper motors, four DC motors, or one stepper and two DC
motors. The currents in each of the output full-bridges, all
N-channel DMOS, are regulated with fixed off-time pulse-width-
modulated (PWM) control circuitry. Each full-bridge peak cur-
rent is set by the value of an external current sense resistor, R
Sx
,
and a reference voltage, V
REFx
.
uses a one-shot circuit to control the time the drivers remain
off. For the A5988 variant, the off-time (t
off
) is 30 µs. For the
A5988-1 variant, t
off
is 8.1 µs.
Fixed Off-Time.
The internal PWM current control circuitry
trolled by a fixed off-time PWM current control circuit that limits
the load current to a desired value, I
TRIP
. Initially, a diagonal pair
of source and sink DMOS outputs are enabled, and current flows
through the motor winding and R
Sx
. When the voltage across the
current sense resistor equals the voltage on the VREFx pin, the
current sense comparator resets the PWM latch, which turns off
the source driver.
The maximum value of current limiting is set by the selection of
R
S
and voltage at the VREF input with a transconductance func-
tion, approximated by:
I
TripMax
= V
REF
/ (3 ×
R
S
)
Each current step is a percentage of the maximum current,
I
TripMax
. The actual current at each step I
Trip
is approximated by:
I
Trip
= (%
I
TripMax
/ 100) ×
I
TripMax
where % I
TripMax
is given in the Step Sequencing table.
Note: It is critical to ensure that the maximum rating of
±500
mV on each SENSEx pin is not exceeded.
Internal PWM Current Control.
Each full-bridge is con-
comparator when the outputs are switched by the internal current
control circuitry. The comparator output is blanked to prevent
false detections of overcurrent conditions due to reverse recovery
currents of the clamp diodes, or to switching transients related to
the capacitance of the load. The stepper blank time, t
BLANK
, is
approximately 1
μs.
Blanking.
This function blanks the output of the current sense
Control Logic.
Communication is implemented via the indus-
try standard I1, I0, and PHASE interface. This communication
logic allows for full, half, and quarter step modes. Each bridge
also has an independent V
REF
input, so higher resolution step
modes can be programmed by dynamically changing the voltage
on the VREFx pins.
generate a gate supply greater than V
BB
to drive the source-side
DMOS gates. A 0.1
μF
ceramic capacitor should be connected
between CP1 and CP2 for pumping purposes. A 0.1
μF
ceramic
capacitor is required between VCP and VBBx to act as a reservoir
to operate the high-side DMOS devices.
Charge Pump (CP1 and CP2)
The charge pump is used to
Shutdown.
In the event of a fault (excessive junction tem-
perature, or low voltage on VCP), the outputs of the device are
disabled until the fault condition is removed. At power-up, the
undervoltage lockout (UVLO) circuit disables the drivers.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
5
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