Low Skew, 1-to18
LVPECL-to-LVCMOS/LVTTL Fanout Buffer
General Description
The ICS83940I-01 is a low skew, 1-to-18 LVPECL-to-LVCMOS/
LVTTL Fanout Buffer. The ICS83940I-01 has two selectable clock
inputs. The PCLK, nPCLK pair can accept LVPECL or SSTL input
levels. The single-ended clock input accepts LVCMOS or LVTTL
input levels.
The ICS83940I-01 is characterized at full 3.3V, full 2.5V and mixed
3.3V input and 2.5V output operating supply modes. Guaranteed
output and part-to-part skew characteristics make the ICS83940I-01
ideal for those clock distribution applications demanding well defined
performance and repeatability.
ICS83940I-01
DATA SHEET
Features
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Eighteen LVCMOS/LVTTL outputs, 23Ω typical output impedance
Selectable LVCMOS_CLK or LVPECL clock inputs
PCLK, nPCLK pair can accept the following differential input
levels: LVPECL, SSTL
LVCMOS_CLK supports the following input types: LVCMOS or
LVTTL
Maximum output frequency: 175MHz
Additive phase jitter, RMS: 0.108ps (typical), 3.3V/3.3V
Output skew: 115ps (maximum)
Part-to-part skew: 800ps (maximum), 3.3V/3.3V
Operating supply modes:
Core/Output
3.3V/3.3V
3.3V/2.5V
2.5V/2.5V
-40°C to 85°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
Block Diagram
CLK_SEL
Pulldown
PCLK
Pulldown
nPCLK
Pullup/Pulldown
Pin Assignment
V
DDO
GND
Q4
Q3
Q0
Q2
Q5
Q1
0
18
32 31 30 29 28 27 26 25
Q[0:17]
GND
GND
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
GND
V
DDO
Q17
Q16
Q15
Q14
Q13
Q12
24
23
Q6
Q7
Q8
V
DDO
Q9
Q10
Q11
GND
LVCMOS_CLK
Pulldown
1
LVCMOS_CLK
CLK_SEL
PCLK
nPCLK
V
DD
V
DDO
ICS83940I-01
22
21
20
19
18
17
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
ICS83940DYI-01 REVISION A SEPTEMBER 27, 2010
1
©2010 Integrated Device Technology, Inc.
ICS83940I-01 Data Sheet
LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS/LVTTL FANOUT BUFFER
Table 1. Pin Descriptions
Number
1, 2, 12, 17, 25
3
4
5
6
7
8, 16, 21, 29
9, 10, 11,
13, 14, 15,
18, 19, 20,
22, 23, 24,
26, 27, 28,
30, 31, 32
Name
GND
LVCMOS_CLK
CLK_SEL
PCLK
nPCLK
V
DD
V
DDO
Q17, Q16, Q15,
Q14, Q13, Q12,
Q11, Q10, Q9,
Q8, Q7, Q6,
Q5, Q4, Q3,
Q2, Q1, Q0
Power
Input
Input
Input
Input
Power
Power
Pulldown
Pulldown
Pulldown
Pullup/
Pulldown
Type
Description
Power supply ground.
Single-ended clock input. LVCMOS/LVTTL interface levels.
Clock select input. When HIGH, selects LVCMOS_CLK input. When LOW,
selects PCLK, nPCLK inputs. LVCMOS / LVTTL interface levels.
Non-inverting differential LVPECL clock input.
Inverting differential LVPECL clock input. V
DD
/2 default when left floating.
Power supply pin.
Output supply pins.
Output
Single-ended clock outputs. LVCMOS/LVTTL interface levels.
NOTE:
Pullup and Pulldown
refers to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLDOWN
R
PULLUP
C
PD
R
OUT
Parameter
Input Capacitance
Input Pulldown Resistor
Input Pullup Resistor
Power Dissipation Capacitance
(per output)
Output Impedance
17
Test Conditions
Minimum
Typical
4
51
51
9
23
28
Maximum
Units
pF
k
Ω
k
Ω
pF
Ω
ICS83940DYI-01 REVISION A SEPTEMBER 27, 2010
2
©2010 Integrated Device Technology, Inc.
ICS83940I-01 Data Sheet
LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS/LVTTL FANOUT BUFFER
Function Tables
Table 3A. Clock Select Function Table
Control Input
CLK_SEL
0
1
PCLK, nPCLK
Selected
De-selected
Clock
LVCMOS_CLK
De-selected
Selected
Table 3B. Clock Input Function Table
Inputs
CLK_SEL
0
0
0
0
0
0
1
1
LVCMOS_CLK
–
–
–
–
–
–
0
1
PCLK
0
1
0
1
Biased; NOTE 1
Biased; NOTE 1
–
–
nPCLK
1
0
Biased; NOTE 1
Biased; NOTE 1
0
1
–
–
Outputs
Q[0:17]
LOW
HIGH
LOW
HIGH
HIGH
LOW
LOW
HIGH
Input to Output Mode
Differential to Single-Ended
Differential to Single-Ended
Single-Ended to Single-Ended
Single-Ended to Single-Ended
Single-Ended to Single-Ended
Single-Ended to Single-Ended
Single-Ended to Single-Ended
Single-Ended to Single-Ended
Polarity
Non-Inverting
Non-Inverting
Non-Inverting
Non-Inverting
Inverting
Inverting
Non-Inverting
Non-Inverting
NOTE 1: Please refer to the Application Information Section,
Wiring the Differential Input to Accept Single-ended Levels.
ICS83940DYI-01 REVISION A SEPTEMBER 27, 2010
3
©2010 Integrated Device Technology, Inc.
ICS83940I-01 Data Sheet
LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS/LVTTL FANOUT BUFFER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Input Current, I
IN
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
Rating
3.6V
-0.3V to V
DD
+ 0.3V
-0.3V to V
DDO
+ 0.3V
±20mA
53.5°C/W (0 mps)
-40°C to 125°C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
DD
= V
DDO
= 3.3V±5%, T
A
= -40°C to 85°C
Symbol
V
DD
V
DDO
I
DD
I
DDO
Parameter
Power Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
No Load
Test Conditions
Minimum
3.135
3.135
Typical
3.3
3.3
Maximum
3.465
3.465
26
28
Units
V
V
mA
mA
Table 4B. Power Supply DC Characteristics,
V
DD
= V
DDO
= 2.5V±5%, T
A
= -40°C to 85°C
Symbol
V
DD
V
DDO
I
DD
I
DDO
Parameter
Power Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
No Load
Test Conditions
Minimum
2.375
2.375
Typical
2.5
2.5
Maximum
2.625
2.625
25
26
Units
V
V
mA
mA
Table 4C. Power Supply DC Characteristics,
V
DD
= 3.3V±5%, V
DDO
= 2.5V±5%, T
A
= -40°C to 85°C
Symbol
V
DD
V
DDO
I
DD
I
DDO
Parameter
Power Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
No Load
Test Conditions
Minimum
3.135
2.375
Typical
3.3
2.5
Maximum
3.465
2.625
26
26
Units
V
V
mA
mA
ICS83940DYI-01 REVISION A SEPTEMBER 27, 2010
4
©2010 Integrated Device Technology, Inc.
ICS83940I-01 Data Sheet
LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS/LVTTL FANOUT BUFFER
Table 4D. LVCMOS DC Characteristics,
V
DD
= 3.3V±5% or 2.5V±5%, V
DDO
= 3.3V±5% or 2.5V±5%, T
A
= -40°C to 85°C
Symbol
V
IH
Parameter
LVCMOS_CLK
Input High Voltage
CLK_SEL
LVCMOS_CLK
V
IL
I
IH
I
IL
V
OH
V
OL
Input Low Voltage
CLK_SEL
Input High Current
Input Low Current
CLK_SEL,
LVCMOS_CLK
CLK_SEL,
LVCMOS_CLK
V
DD
= 3.3V or 2.5V
V
DD
= 3.3V or 2.5V
V
DD
= 3.3V or 2.5V
V
DD
= V
IN
= 3.465V or 2.625V
V
DD
= 3.465V or 2.625V, V
IN
= 0V
V
DDO
= 3.465V
V
DDO
= 2.625V
Output Low Voltage; NOTE 1
V
DDO
= 3.465V or 2.65V
-5
2.8
2.1
0.55
2
-0.3
-0.3
V
DD
+ 0.3
1.3
0.8
150
V
V
V
µA
µA
V
V
V
Test Conditions
Minimum
Typical
Maximum
Units
Output High Voltage; NOTE 1
NOTE 1: Outputs terminated with 50
Ω
to V
DDO
/2. See Parameter Measurement Information section,
Output Load Test Circuit diagram.
Table 4E. LVPECL DC Characteristics,
V
DD
= V
DDO
= 3.3V±5%, T
A
= -40°C to 85°C
Symbol
I
IH
I
IL
I
IN
V
PP
V
CMR
Parameter
Input High Current
Input Low Current
nPCLK
Input Current
Peak-to-Peak Input Voltage
Common Mode Input Voltage; NOTE 1
500
V
DD
– 1.4
PCLK, nPCLK
PCLK
Test Conditions
V
DD
= V
IN
= 3.465V or 2.625V
V
DD
= 3.465V or 2.625V, V
IN
= 0V
V
DD
= 3.465V or 2.625V, V
IN
= 0V
-10
-150
±200
1000
V
DD
– 0.6
Minimum
Typical
Maximum
150
Units
µA
µA
µA
µA
mV
V
NOTE 1: Common mode voltage is defined as V
IH
.
Table 4F. LVPECL DC Characteristics,
V
DD
= 3.3V±5% or 2.5V±5%, V
DDO
= 2.5V±5%, T
A
= -40°C to 85°C
Symbol
I
IH
I
IL
I
IN
V
PP
V
CMR
Parameter
Input High Current
Input Low Current
nPCLK
Input Current
Peak-to-Peak Input Voltage
Common Mode Input Voltage; NOTE 1
300
V
DD
– 1.4
PCLK, nPCLK
PCLK
Test Conditions
V
DD
= V
IN
= 3.465V or 2.625V
V
DD
= 3.465V or 2.625V, V
IN
= 0V
V
DD
= 3.465V or 2.625V, V
IN
= 0V
-10
-150
±200
1000
V
DD
– 0.6
Minimum
Typical
Maximum
150
Units
µA
µA
µA
µA
mV
V
NOTE 1: Common mode voltage is defined as V
IH
.
ICS83940DYI-01 REVISION A SEPTEMBER 27, 2010
5
©2010 Integrated Device Technology, Inc.
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