74HC174; 74HCT174
Hex D-type flip-flop with reset; positive-edge trigger
Rev. 4 — 12 May 2016
Product data sheet
1. General description
The 74HC174; 74HCT174 are hex positive edge-triggered D-type flip-flops with individual
data inputs (Dn) and outputs (Qn). The common clock (CP) and master reset (MR) inputs
load and reset all flip-flops simultaneously. The D-input that meets the set-up and hold
time requirements on the LOW-to-HIGH clock transition is stored in the flip-flop and
appears at the Q output. A LOW on MR causes the flip-flops and outputs to be reset LOW.
Inputs include clamp diodes. This enables the use of current limiting resistors to interface
inputs to voltages in excess of V
CC
.
2. Features and benefits
Input levels:
For 74HC174: CMOS level
For 74HCT174: TTL level
Six edge-triggered D-type flip-flops
Asynchronous master reset
Complies with JEDEC standard no. 7A
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V.
Multiple package options
Specified from
40 C
to +85
C
and
40 C
to +125
C.
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74HC174D
74HCT174D
74HC174DB
74HCT174DB
74HC174PW
74HCT174PW
40 C
to +125
C
40 C
to +125
C
SSOP16
plastic shrink small outline package; 16 leads; body width
5.3 mm
SOT338-1
SOT403-1
40 C
to +125
C
Name
SO16
Description
Version
plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
Type number
TSSOP16 plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
Nexperia
74HC174; 74HCT174
Hex D-type flip-flop with reset; positive-edge trigger
4. Functional diagram
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
Fig 3.
Logic diagram
74HC_HCT174
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 4 — 12 May 2016
2 of 17
Nexperia
74HC174; 74HCT174
Hex D-type flip-flop with reset; positive-edge trigger
5. Pinning information
5.1 Pinning
Fig 4.
Pin configuration SO16
Fig 5.
Pin configuration SSOP16 and TSSOP16
5.2 Pin description
Table 2.
Symbol
MR
Q0 to Q5
D0 to D5
GND
CP
V
CC
Pin description
Pin
1
2, 5, 7, 10, 12, 15
3, 4, 6, 11, 13, 14
8
9
16
Description
asynchronous master reset input (active LOW)
flip-flop output
data input
ground (0 V)
clock input (LOW-to-HIGH edge-triggered)
positive supply voltage
74HC_HCT174
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 4 — 12 May 2016
3 of 17
Nexperia
74HC174; 74HCT174
Hex D-type flip-flop with reset; positive-edge trigger
6. Functional description
Table 3.
Function table
[1]
Inputs
MR
reset (clear)
load “1”
load “0”
[1]
Operating modes
Outputs
CP
X
Dn
X
h
l
Qn
L
H
L
L
H
H
H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition;
X = don’t care;
= LOW-to-HIGH clock transition.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V)
Symbol
V
CC
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
Parameter
supply voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
T
amb
=
40 C
to +125
C
SO16, SSOP16 and TSSOP16
[1]
[2]
[2]
Conditions
V
I
<
0.5
V or V
I
> V
CC
+ 0.5 V
V
O
<
0.5
V or V
O
> V
CC
+ 0.5 V
0.5
V < V
O
< V
CC
+ 0.5 V
[1]
[1]
Min
0.5
-
-
-
-
50
65
-
Max
+7
20
20
25
50
-
+150
500
Unit
V
mA
mA
mA
mA
mA
C
mW
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
For SO16 package: above 70
C
the value of P
tot
derates linearly with 8 mW/K.
For SSOP16 and TSSOP16 packages: above 60
C
the value of P
tot
derates linearly with 5.5 mW/K.
74HC_HCT174
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 4 — 12 May 2016
4 of 17
Nexperia
74HC174; 74HCT174
Hex D-type flip-flop with reset; positive-edge trigger
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V)
Symbol Parameter
V
CC
V
I
V
O
T
amb
t/V
supply voltage
input voltage
output voltage
ambient temperature
input transition rise and fall rate
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
Conditions
Min
2.0
0
0
40
-
-
-
74HC174
Typ
5.0
-
-
-
-
1.67
-
Max
6.0
V
CC
V
CC
+125
625
139
83
Min
4.5
0
0
40
-
-
-
74HCT174
Typ
5.0
-
-
-
-
1.67
-
Max
5.5
V
CC
V
CC
+125
-
139
-
V
V
V
C
ns/V
ns/V
ns/V
Unit
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
74HC174
V
IH
HIGH-level
input voltage
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
V
IL
LOW-level
input voltage
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
V
OH
HIGH-level
output voltage
V
I
= V
IH
or V
IL
I
O
=
20 A;
V
CC
= 2.0 V
I
O
=
20 A;
V
CC
= 4.5 V
I
O
=
20 A;
V
CC
= 6.0 V
I
O
=
4.0
mA; V
CC
= 4.5 V
I
O
=
5.2
mA; V
CC
= 6.0 V
V
OL
LOW-level
output voltage
V
I
= V
IH
or V
IL
I
O
= 20
A;
V
CC
= 2.0 V
I
O
= 20
A;
V
CC
= 4.5 V
I
O
= 20
A;
V
CC
= 6.0 V
I
O
= 4.0 mA; V
CC
= 4.5 V
I
O
= 5.2 mA; V
CC
= 6.0 V
I
I
I
CC
input leakage
current
supply current
V
I
= V
CC
or GND;
V
CC
= 6.0 V
V
I
= V
CC
or GND; I
O
= 0 A;
V
CC
= 6.0 V
-
-
-
-
-
-
-
0
0
0
0.15
0.16
-
-
0.1
0.1
0.1
0.26
0.26
0.1
8.0
-
-
-
-
-
-
-
0.1
0.1
0.1
0.33
0.33
1
80
-
-
-
-
-
-
-
0.1
0.1
0.1
0.4
0.4
1
160
V
V
V
V
V
A
A
1.9
4.4
5.9
3.98
5.48
2.0
4.5
6.0
4.32
5.81
-
-
-
-
-
1.9
4.4
5.9
3.84
5.34
-
-
-
-
-
1.9
4.4
5.9
3.7
5.2
-
-
-
-
-
V
V
V
V
V
1.5
3.15
4.2
-
-
-
1.2
2.4
3.2
0.8
2.1
2.8
-
-
-
0.5
1.35
1.8
1.5
3.15
4.2
-
-
-
-
-
-
0.5
1.35
1.8
1.5
3.15
4.2
-
-
-
-
-
-
0.5
1.35
1.8
V
V
V
V
V
V
Conditions
Min
25
C
Typ
Max
40 C
to +85
C 40 C
to +125
C
Unit
Min
Max
Min
Max
74HC_HCT174
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 4 — 12 May 2016
5 of 17
Embedded System
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