EEWORLDEEWORLDEEWORLD

Part Number

Search

552AF000147DG

Description
VCXO; DIFF/SE; DUAL FREQ; 10-141
CategoryPassive components    oscillator   
File Size477KB,15 Pages
ManufacturerSilicon Laboratories Inc
Environmental Compliance
Download Datasheet Parametric View All

552AF000147DG Online Shopping

Suppliers Part Number Price MOQ In stock  
552AF000147DG - - View Buy Now

552AF000147DG Overview

VCXO; DIFF/SE; DUAL FREQ; 10-141

552AF000147DG Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerSilicon Laboratories Inc
package instructionROHS COMPLIANT PACKAGE-6
Reach Compliance Codecompliant
Other featuresTRAY
Maximum control voltage3.3 V
Minimum control voltage
maximum descent time0.35 ns
Frequency Adjustment - MechanicalNO
Frequency offset/pull rate100 ppm
frequency stability50%
linearity10%
Manufacturer's serial numberSI552
Installation featuresSURFACE MOUNT
Number of terminals6
Maximum operating frequency945 MHz
Minimum operating frequency10 MHz
Nominal operating frequency704.38058 MHz
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Oscillator typeLVPECL
Package body materialPLASTIC/EPOXY
Encapsulate equivalent codeDILCC6,.2
physical size7.0mm x 5.0mm x 1.85mm
power supply3.3 V
Certification statusNot Qualified
longest rise time0.35 ns
Maximum slew rate130 mA
Maximum supply voltage3.63 V
Minimum supply voltage2.97 V
Nominal supply voltage3.3 V
surface mountYES
maximum symmetry55/45 %
Si 5 5 2
R
EVISION
D
D
U A L
F
REQUENCY
V
OLTAGE
- C
ON TROLLED
C
R Y S TA L
O
SCILLATOR
(VCXO) 10 MH
Z TO
1 . 4 G H
Z
Features
Available with any-rate output
frequencies from 10–945 MHz and
selected frequencies to 1.4 GHz
Two selectable output frequencies
3rd generation DSPLL
®
with superior
jitter performance
3x better frequency stability than
SAW-based oscillators
Internal fixed crystal frequency
ensures high reliability and low
aging
Available CMOS, LVPECL,
LVDS, and CML outputs
3.3, 2.5, and 1.8 V supply options
Industry-standard 5 x 7 mm
package and pinout
Pb-free/RoHS-compliant
Si5602
Applications
SONET/SDH
xDSL
10 GbE LAN/WAN
Ordering Information:
Low-jitter clock generation
Optical modules
Clock and data recovery
See page 10.
Description
The Si552 dual-frequency VCXO utilizes Silicon Laboratories’ advanced
DSPLL
®
circuitry to provide a very low jitter clock for all output frequencies.
The Si552 is available with any-rate output frequency from 10 to 945 MHz
and selected frequencies to 1400 MHz. Unlike traditional VCXOs, where a
different crystal is required for each output frequency, the Si552 uses one
fixed crystal frequency to provide a wide range of output frequencies. This
IC-based approach allows the crystal resonator to provide exceptional
frequency stability and reliability. In addition, DSPLL clock synthesis
provides superior supply noise rejection, simplifying the task of generating
low-jitter clocks in noisy environments typically found in communication
systems. The Si552 IC-based VCXO is factory-configurable for a wide
variety of user specifications including frequency, supply voltage, output
format, tuning slope, and temperature stability. Specific configurations are
factory programmed at time of shipment, thereby eliminating the long lead
times associated with custom oscillators.
Pin Assignments:
See page 9.
(Top View)
V
C
1
2
3
6
5
4
V
DD
FS
GND
CLK–
CLK+
Functional Block Diagram
V
DD
CLK- CLK+
Fixed
Frequency XO
Any-rate
10–1400 MHz
DSPLL
®
Clock Synthesis
ADC
V
C
FS
GND
Rev. 1.2 6/18
Copyright © 2018 by Silicon Laboratories
Si552
Thermometer Thesis
Thermometer Thesis...
xhe332523 MCU
SMT Standards Collection Catalog
The process requirements for mounting SMD on flexible printed circuit boards (FPCs)As electronic products are miniaturized, a considerable number of consumer products are mounted on the surface of FPC...
szlrsmt PCB Design
STM8S105K4TIM2 application problems
Configure like this:TIM2_PSCR |= TIM2_Prescaler;TIM2_CNTRH = (INT8U)(TIM2_Period >> 8);TIM2_CNTRL = (INT8U)(TIM2_Period);/* Set the Autoreload value */TIM2_ARRH = (INT8U)(TIM2_Period >> 8);TIM2_ARRL =...
lj1978 stm32/stm8
[FPGA entry to actual combat] Hands-on explanation of the internal principle of asynchronous FIFO 2; Source code & Q&A
[FPGA entry to actual combat] Hands-on explanation of the internal principles of asynchronous FIFO 2; Students who do not understand the knowledge points in the video can ask questions in the forum, a...
尤老师 FPGA/CPLD
Is it useful to take the registered electrical engineer exam now?
I want to take the test, and I heard it is useful. If it is useful, it is worth a try. If anyone knows the answer, please help me....
wanghlady Talking
Multisim Circuit System Design and Simulation Tutorial
"Multisim Circuit System Design and Simulation Tutorial" combines a large number of examples to introduce the basic operations, advanced functions, component libraries, various instruments, and circui...
arui1999 Download Centre

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 2555  2547  1166  1001  2279  52  24  21  46  30 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号